| Age | Commit message (Expand) | Author |
|---|
| 2022-05-20 | RISC-V: Remove RV128-only fmv instructions | Tsukasa OI |
| 2022-05-18 | x86: shrink op_riprel | Jan Beulich |
| 2022-05-17 | RISC-V: Added half-precision floating-point v1.0 instructions. | Nelson Chu |
| 2022-05-12 | cgen: increase buffer for hash_insn_list | Alan Modra |
| 2022-05-11 | opcodes cgen: remove use of PTR | Alan Modra |
| 2022-05-10 | opcodes: remove use of PTR | Alan Modra |
| 2022-05-07 | Fix multiple ubsan warnings in i386-dis.c | Alan Modra |
| 2022-05-05 | Move TILE-Gx files to TARGET64_LIBOPCODES_CFILES | Luis Machado |
| 2022-05-05 | Don't define ARCH_cris for BFD64 | Luis Machado |
| 2022-05-05 | IBM zSystems: mgrk, mg first operand requires register pair | Andreas Krebbel |
| 2022-04-30 | opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblers | Thomas Hebb |
| 2022-04-27 | x86: VFPCLASSSH is Evex.LLIG | Jan Beulich |
| 2022-04-19 | x86: VCMPSH is Evex.LLIG | Jan Beulich |
| 2022-04-19 | x86: drop stray CheckRegSize from VFPCLASSPH | Jan Beulich |
| 2022-04-19 | x86: correct and simplify NOP disassembly | Jan Beulich |
| 2022-04-07 | IBM zSystems: Add support for z16 as CPU name. | Andreas Krebbel |
| 2022-04-04 | opcodes/i386: partially implement disassembler style support | Andrew Burgess |
| 2022-04-04 | opcodes/riscv: implement style support in the disassembler | Andrew Burgess |
| 2022-04-04 | objdump/opcodes: add syntax highlighting to disassembler output | Andrew Burgess |
| 2022-03-31 | x86: Remove bfd_arch_l1om and bfd_arch_k1om | H.J. Lu |
| 2022-03-31 | aarch64: Relax check for RNG system registers | Richard Sandiford |
| 2022-03-29 | RISC-V: correct FCVT.Q.L[U] | Jan Beulich |
| 2022-03-25 | libtool.m4: fix the NM="/nm/over/here -B/option/with/path" case | Nick Alcock |
| 2022-03-24 | x86: drop L1OM special case from disassembler | Jan Beulich |
| 2022-03-20 | gas:LoongArch: Fix segment error in compilation due to too long symbol name. | liuzhensong |
| 2022-03-20 | ubsan: loongarch : signed integer shift overflow. | liuzhensong |
| 2022-03-18 | x86: also fold remaining multi-vector-size shift insns | Jan Beulich |
| 2022-03-18 | x86: drop stray CheckRegSize from VEXTRACT{F,I}32X4 | Jan Beulich |
| 2022-03-18 | x86: fold certain AVX2 templates into their AVX counterparts | Jan Beulich |
| 2022-03-18 | RISC-V: Cache management instructions | Tsukasa OI |
| 2022-03-18 | RISC-V: Prefetch hint instructions and operand set | Tsukasa OI |
| 2022-03-17 | x86: never set i386_cpu_flags' "unused" field | Jan Beulich |
| 2022-03-17 | x86: unify CPU flag on/off processing | Jan Beulich |
| 2022-03-17 | x86: drop L1OM/K1OM support from gas | Jan Beulich |
| 2022-03-17 | x86: assorted IAMCU CPU checking fixes | Jan Beulich |
| 2022-03-16 | opcodes: handle bfd_amdgcn_arch in configure script | Simon Marchi |
| 2022-03-16 | Delete PowerPC macro insn support | Alan Modra |
| 2022-03-16 | PowerPC SPE/SPE2 aliases in powerpc_macros | Alan Modra |
| 2022-03-16 | PowerPC VLE extended instructions in powerpc_macros | Alan Modra |
| 2022-03-16 | PowerPC32 extended instructions in powerpc_macros | Alan Modra |
| 2022-03-16 | PowerPC64 extended instructions in powerpc_macros | Alan Modra |
| 2022-03-14 | PR28959, obdump doesn't disassemble mftb instruction | Alan Modra |
| 2022-03-06 | MIPS/opcodes: Fix alias annotation for branch instructions | Maciej W. Rozycki |
| 2022-02-25 | RISC-V: Fix mask for some fcvt instructions | Tsukasa OI |
| 2022-02-17 | Updated Serbian translations for the bfd, gold, ld and opcodes directories | Nick Clifton |
| 2022-02-15 | x86: Add has_sib to struct instr_info | H.J. Lu |
| 2022-02-14 | microblaze: fix fsqrt collicion to build on glibc-2.35 | Sergei Trofimovich |
| 2022-01-24 | Update Bulgarian, French, Romaniam and Ukranian translation for some of the s... | Nick Clifton |
| 2022-01-23 | Regenerate Makefile.in files with automake 1.15.1 | H.J. Lu |
| 2022-01-23 | Regenerate configure files with autoconf 2.69 | H.J. Lu |
