ci/binutils-gdb.git - [no description]

Age	Commit message (Expand)	Author
2022-08-02	arm: Add cfi expression support for ra_auth_code	Victor Do Nascimento
2022-08-02	arm: Use DWARF numbering convention for pseudo-register representation	Victor Do Nascimento
2022-08-01	x86: SKINIT with operand needs IgnoreSize	Jan Beulich
2022-08-01	opcodes: LoongArch: add "ret" instruction to reduce typing	WANG Xuerui
2022-08-01	opcodes: LoongArch: make all non-native jumps desugar to canonical b{lt/ge}[u...	WANG Xuerui
2022-08-01	Get rid of fprintf_vma and sprintf_vma	Alan Modra
2022-07-29	Arm64: re-work PR gas/27217 fix	Jan Beulich
2022-07-29	RISC-V: Add `OP_V' to .insn named opcodes	Tsukasa OI
2022-07-25	LoongArch: Add testcases for new relocate types.	liuzhensong
2022-07-21	x86/Intel: correct AVX512F scatter insn element sizes	Jan Beulich
2022-07-21	PR29390, DW_CFA_AARCH64_negate_ra_state vs. DW_CFA_GNU_window_save	Alan Modra
2022-07-18	x86: correct VMOVSH attributes	Jan Beulich
2022-07-14	PowerPC: implement md_operand to parse register names	Alan Modra
2022-07-09	gas: arm -mwarn-syms duplicates	Alan Modra
2022-07-07	RISC-V: Added Zfhmin and Zhinxmin.	Tsukasa OI
2022-07-07	RISC-V: Fix disassembling Zfinx with -M numeric	Tsukasa OI
2022-07-07	RISC-V: Fix requirement handling on Zhinx+{D,Q}	Tsukasa OI
2022-07-06	x86: fix 3-operand insn reverse-matching	Jan Beulich
2022-07-06	x86: introduce a state stack for .arch	Jan Beulich
2022-07-06	x86: permit "default" with .arch	Jan Beulich
2022-07-04	gas/testsuite: properly exclude aout in all/weakref1u	Jan Beulich
2022-07-04	x86-64: improve handling of branches to absolute addresses	Jan Beulich
2022-06-29	opcodes/aarch64: split off creation of comment text in disassembler	Andrew Burgess
2022-06-28	RISC-V: Add 'Sstc' extension and its CSRs	Tsukasa OI
2022-06-28	RISC-V: Add 'Sscofpmf' extension with its CSRs	Tsukasa OI
2022-06-28	RISC-V: Add 'Smstateen' extension and its CSRs	Tsukasa OI
2022-06-27	drop XC16x bits	Jan Beulich
2022-06-22	RISC-V: Reorder the prefixed extensions which are out of order.	Nelson Chu
2022-06-22	RISC-V: Use single h extension to control hypervisor CSRs and instructions.	Nelson Chu
2022-06-16	Restore readelf -wF	Alan Modra
2022-06-16	PR29250, readelf erases CIE initial register state	Alan Modra
2022-06-03	x86: exclude certain ISA extensions from v3/v4 ISA	Jan Beulich
2022-05-31	Trailing spaces in objdump -r header	Alan Modra
2022-05-30	Fix failing test for armeb-gnu-eabi	Luis Machado
2022-05-30	RISC-V: Add zhinx extension supports.	jiawei
2022-05-27	opcodes/i386: remove trailing whitespace from insns with zero operands	Andrew Burgess
2022-05-27	x86/Intel: allow MASM representation of embedded rounding / SAE	Jan Beulich
2022-05-27	x86: re-work AVX512 embedded rounding / SAE	Jan Beulich
2022-05-27	x86/Intel: adjust representation of embedded rounding / SAE	Jan Beulich
2022-05-27	x86/Intel: allow MASM representation of embedded broadcast	Jan Beulich
2022-05-27	x86/Intel: adjust representation of embedded broadcast	Jan Beulich
2022-05-25	RISC-V: Fix RV32Q conflict	Tsukasa OI
2022-05-25	opcodes: introduce BC field; fix isel	Dmitry Selyutin
2022-05-20	RISC-V: Update zfinx implement with zicsr.	Jia-Wei Chen
2022-05-20	RISC-V: Remove RV128-only fmv instructions	Tsukasa OI
2022-05-19	arm: Fix system register fpcxt_ns and fpcxt_s naming convention.	Srinath Parvathaneni
2022-05-18	arm: Add unwind support for mixed register lists	Victor Do Nascimento
2022-05-18	gas: avoid octal numbers being accepted when processing .linefile	Jan Beulich
2022-05-18	gas: avoid bignum related errors when processing .linefile	Jan Beulich
2022-05-18	gas: don't ignore .linefile inside false conditionals	Jan Beulich