diff options
| author | Jia-Wei Chen <jiawei@iscas.ac.cn> | 2022-05-20 18:09:34 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-05-20 22:21:34 +0800 |
| commit | 9ecdcd1be1e8487fca035c588d17a102d1f8b5eb (patch) | |
| tree | fa5e828a740a04146ca88a35c2bdb212516afea6 /opcodes | |
| parent | aa8c9d60a6fc8865a5c4131aab243bf97b961e2c (diff) | |
RISC-V: Update zfinx implement with zicsr.
Update zfinx implement with zicsr, fix missing fcsr use by zfinx.
add zicsr imply by zfinx.
bfd/ChangeLog:
* elfxx-riscv.c: New imply.
gas/ChangeLog:
* testsuite/gas/riscv/csr-insns-pseudo-zfinx.d: New test.
opcodes/ChangeLog:
* riscv-opc.c: Update insn class.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index eaba3cb46c..bbd4a3718f 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -638,22 +638,22 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.h.lu", 64, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, /* Single-precision floating-point instruction subset. */ -{"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, -{"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, -{"fscsr", 0, INSN_CLASS_F, "s", MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS }, -{"fscsr", 0, INSN_CLASS_F, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, -{"fssr", 0, INSN_CLASS_F, "s", MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS }, -{"fssr", 0, INSN_CLASS_F, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, -{"frrm", 0, INSN_CLASS_F, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS }, -{"fsrm", 0, INSN_CLASS_F, "s", MATCH_FSRM, MASK_FSRM|MASK_RD, match_opcode, INSN_ALIAS }, -{"fsrm", 0, INSN_CLASS_F, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS }, -{"fsrmi", 0, INSN_CLASS_F, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS }, -{"fsrmi", 0, INSN_CLASS_F, "Z", MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS }, +{"frcsr", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, +{"frsr", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, +{"fscsr", 0, INSN_CLASS_F_OR_ZFINX, "s", MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS }, +{"fscsr", 0, INSN_CLASS_F_OR_ZFINX, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, +{"fssr", 0, INSN_CLASS_F_OR_ZFINX, "s", MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS }, +{"fssr", 0, INSN_CLASS_F_OR_ZFINX, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, +{"frrm", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS }, +{"fsrm", 0, INSN_CLASS_F_OR_ZFINX, "s", MATCH_FSRM, MASK_FSRM|MASK_RD, match_opcode, INSN_ALIAS }, +{"fsrm", 0, INSN_CLASS_F_OR_ZFINX, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS }, +{"fsrmi", 0, INSN_CLASS_F_OR_ZFINX, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS }, +{"fsrmi", 0, INSN_CLASS_F_OR_ZFINX, "Z", MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS }, {"frflags", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS }, {"fsflags", 0, INSN_CLASS_F_OR_ZFINX, "s", MATCH_FSFLAGS, MASK_FSFLAGS|MASK_RD, match_opcode, INSN_ALIAS }, -{"fsflags", 0, INSN_CLASS_F, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS }, -{"fsflagsi", 0, INSN_CLASS_F, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS }, -{"fsflagsi", 0, INSN_CLASS_F, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS }, +{"fsflags", 0, INSN_CLASS_F_OR_ZFINX, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS }, +{"fsflagsi", 0, INSN_CLASS_F_OR_ZFINX, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS }, +{"fsflagsi", 0, INSN_CLASS_F_OR_ZFINX, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS }, {"flw", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"flw", 0, INSN_CLASS_F, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, |