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| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-12-02 15:00:57 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-12-02 15:00:57 +0000 |
| commit | a5e9beead8580777ea4886b06c493a6f79570f93 (patch) | |
| tree | 431281e2d3691b7a3a2d67238d2aac7d0dfadcf3 /opcodes/aarch64-opc.c | |
| parent | e14c9cb6c88e3dbcbaef4e0f62f8e07ece17b51b (diff) | |
aarch64: Add Armv8.8-A system registers
Armv8.8-A defines two new system registers: allint and icc_nmiar1_el1.
Both of them were previously unmapped. allint supports a 0/1 immediate.
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ALLINT--All-Interrupt-Mask-Bit?lang=en]
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ICC-NMIAR1-EL1--Interrupt-Controller-Non-maskable-Interrupt-Acknowledge-Register-1?lang=en]
opcodes/
* aarch64-opc.c (SR_V8_8): New macro.
(aarch64_sys_regs): Add allint and icc_nmiar1_el1.
(aarch64_pstatefields): Add allint.
gas/
* testsuite/gas/aarch64/armv8_8-a-sysregs.s,
* testsuite/gas/aarch64/armv8_8-a-sysregs.d: New test.
* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.s,
* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.l,
* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.d: New test.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 9b7d7efd43..a77070e187 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3975,6 +3975,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, #define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4) #define SR_V8_6(n,e,f) SR_FEAT (n,e,f,V8_6) #define SR_V8_7(n,e,f) SR_FEAT (n,e,f,V8_7) +#define SR_V8_8(n,e,f) SR_FEAT (n,e,f,V8_8) /* Has no separate libopcodes feature flag, but separated out for clarity. */ #define SR_GIC(n,e,f) SR_CORE (n,e,f) /* Has no separate libopcodes feature flag, but separated out for clarity. */ @@ -5000,6 +5001,9 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_V8_7 ("pmsnevfr_el1", CPENC (3,0,C9,C9,1), 0), SR_V8_7 ("hcrx_el2", CPENC (3,4,C1,C2,2), 0), + SR_V8_8 ("allint", CPENC (3,0,C4,C3,0), 0), + SR_V8_8 ("icc_nmiar1_el1", CPENC (3,0,C12,C9,5), F_REG_READ), + { 0, CPENC (0,0,0,0,0), 0, 0 } }; @@ -5032,6 +5036,7 @@ const aarch64_sys_reg aarch64_pstatefields [] = | F_REG_MAX_VALUE (1)), SR_SME ("svcrsmza", 0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x6,0x1) | F_REG_MAX_VALUE (1)), + SR_V8_8 ("allint", 0x08, F_REG_MAX_VALUE (1)), { 0, CPENC (0,0,0,0,0), 0, 0 }, }; |