diff options
| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-03-12 14:18:59 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-03-12 14:20:46 +0000 |
| commit | 7fce7ea986bc66d4af3c21d4f6ab2a987f3aac46 (patch) | |
| tree | 08c07d9e7fde9270e9257a54796fc0df721abe83 /opcodes/aarch64-opc.c | |
| parent | 203a206d14e4892bc4ab9448e08617506b5d613d (diff) | |
aarch64: Add few missing system registers
This patch adds few missing system registers to GAS: LORC_EL1,
LOREA_EL1, LORN_EL1, LORSA_EL1, ICC_CTLR_EL3, ICC_SRE_ELX, ICH_VTR_EL2.
gas/ChangeLog:
2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/illegal-sysreg-7.d: New test.
* testsuite/gas/aarch64/illegal-sysreg-7.l: New test.
* testsuite/gas/aarch64/illegal-sysreg-7.s: New test.
* testsuite/gas/aarch64/sysreg-7.d: New test.
* testsuite/gas/aarch64/sysreg-7.s: New test.
opcodes/ChangeLog:
2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 50d6412393..521ec6f9c8 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4570,6 +4570,16 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("csrptr_el2", CPENC (2,4,C8,C0,1), 0), SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3), F_REG_READ), + SR_CORE ("lorc_el1", CPENC (3,0,C10,C4,3), 0), + SR_CORE ("lorea_el1", CPENC (3,0,C10,C4,1), 0), + SR_CORE ("lorn_el1", CPENC (3,0,C10,C4,2), 0), + SR_CORE ("lorsa_el1", CPENC (3,0,C10,C4,0), 0), + SR_CORE ("icc_ctlr_el3", CPENC (3,6,C12,C12,4), 0), + SR_CORE ("icc_sre_el1", CPENC (3,0,C12,C12,5), 0), + SR_CORE ("icc_sre_el2", CPENC (3,4,C12,C9,5), 0), + SR_CORE ("icc_sre_el3", CPENC (3,6,C12,C12,5), 0), + SR_CORE ("ich_vtr_el2", CPENC (3,4,C12,C11,1), F_REG_READ), + SR_CORE ("brbcr_el1", CPENC (2,1,C9,C0,0), 0), SR_CORE ("brbcr_el12", CPENC (2,5,C9,C0,0), 0), SR_CORE ("brbfcr_el1", CPENC (2,1,C9,C0,1), 0), |