diff options
| author | Alex Coplan <alex.coplan@arm.com> | 2020-08-12 13:49:54 +0100 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2020-08-12 13:53:17 +0100 |
| commit | 2e49fd1edf34d7a1db5944ee57071571a0556811 (patch) | |
| tree | 66388b3b693cf4af509e99a79180086c17d7543a /opcodes/aarch64-opc.c | |
| parent | 369afd5008c6c8aa828065090c12001b9ffa7c53 (diff) | |
aarch64: Add support for MPAM system registers
This patch adds support for the system registers introduced in the
Armv8-A MPAM extension.
See https://developer.arm.com/documentation/ddi0598/latest for the
Arm ARM supplement documenting this extension.
gas/ChangeLog:
* testsuite/gas/aarch64/mpam-bad.d: New test.
* testsuite/gas/aarch64/mpam-bad.l: Error output.
* testsuite/gas/aarch64/mpam-bad.s: Input.
* testsuite/gas/aarch64/mpam.d: New test.
* testsuite/gas/aarch64/mpam.s: Input.
opcodes/ChangeLog:
* aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index d2b325f15b..5534dc7fde 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4241,6 +4241,23 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_V8_4 ("sder32_el2", CPENC (3,4,C1,C3,1), 0), SR_V8_4 ("vncr_el2", CPENC (3,4,C2,C2,0), 0), + SR_CORE ("mpam0_el1", CPENC (3,0,C10,C5,1), 0), + SR_CORE ("mpam1_el1", CPENC (3,0,C10,C5,0), 0), + SR_CORE ("mpam1_el12", CPENC (3,5,C10,C5,0), 0), + SR_CORE ("mpam2_el2", CPENC (3,4,C10,C5,0), 0), + SR_CORE ("mpam3_el3", CPENC (3,6,C10,C5,0), 0), + SR_CORE ("mpamhcr_el2", CPENC (3,4,C10,C4,0), 0), + SR_CORE ("mpamidr_el1", CPENC (3,0,C10,C4,4), F_REG_READ), + SR_CORE ("mpamvpm0_el2", CPENC (3,4,C10,C6,0), 0), + SR_CORE ("mpamvpm1_el2", CPENC (3,4,C10,C6,1), 0), + SR_CORE ("mpamvpm2_el2", CPENC (3,4,C10,C6,2), 0), + SR_CORE ("mpamvpm3_el2", CPENC (3,4,C10,C6,3), 0), + SR_CORE ("mpamvpm4_el2", CPENC (3,4,C10,C6,4), 0), + SR_CORE ("mpamvpm5_el2", CPENC (3,4,C10,C6,5), 0), + SR_CORE ("mpamvpm6_el2", CPENC (3,4,C10,C6,6), 0), + SR_CORE ("mpamvpm7_el2", CPENC (3,4,C10,C6,7), 0), + SR_CORE ("mpamvpmv_el2", CPENC (3,4,C10,C4,1), 0), + { 0, CPENC (0,0,0,0,0), 0, 0 } }; |