diff options
| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-01-11 19:14:02 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-03-18 15:32:22 +0800 |
| commit | 41d6ac5da655a2e78109848f2db47e53552fd61a (patch) | |
| tree | 2d6c789b0169492700e80edbde84342c9c4bb68c /include | |
| parent | 3b374308d3006407b9571e573e4ccce4e904a4c4 (diff) | |
RISC-V: Cache management instructions
This commit adds 'Zicbom' / 'Zicboz' instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction classes.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add cache-block management
instructions.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 9 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 2 |
2 files changed, 11 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 1572c84f0b..3eea33a5da 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2036,6 +2036,15 @@ #define MASK_PREFETCH_R 0x1f07fff #define MATCH_PREFETCH_W 0x306013 #define MASK_PREFETCH_W 0x1f07fff +/* Zicbom/Zicboz instructions. */ +#define MATCH_CBO_CLEAN 0x10200f +#define MASK_CBO_CLEAN 0xfff07fff +#define MATCH_CBO_FLUSH 0x20200f +#define MASK_CBO_FLUSH 0xfff07fff +#define MATCH_CBO_INVAL 0x200f +#define MASK_CBO_INVAL 0xfff07fff +#define MATCH_CBO_ZERO 0x40200f +#define MASK_CBO_ZERO 0xfff07fff /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 5462b5ecea..b769769b4e 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -388,7 +388,9 @@ enum riscv_insn_class INSN_CLASS_V, INSN_CLASS_ZVEF, INSN_CLASS_SVINVAL, + INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, + INSN_CLASS_ZICBOZ, }; /* This structure holds information for a particular instruction. */ |