diff options
| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-01-11 19:14:02 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-03-18 15:32:16 +0800 |
| commit | 3b374308d3006407b9571e573e4ccce4e904a4c4 (patch) | |
| tree | 96bfce86a830f793e0ef73924c4b3c1b3788b68a /include | |
| parent | 5fac3f02edacfca458f7eeaaaa33a87e26e0e332 (diff) | |
RISC-V: Prefetch hint instructions and operand set
This commit adds 'Zicbop' hint instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction class.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add handling for new operand
type 'f' (32-byte aligned pseudo S-type immediate for prefetch
hints).
(validate_riscv_insn): Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
MASK_PREFETCH_W): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class INSN_CLASS_ZICBOP.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add handling for new operand
type.
* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 7 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 01cd3a4e9d..1572c84f0b 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2029,6 +2029,13 @@ #define MASK_HSV_W 0xfe007fff #define MATCH_HSV_D 0x6e004073 #define MASK_HSV_D 0xfe007fff +/* Zicbop hint instructions. */ +#define MATCH_PREFETCH_I 0x6013 +#define MASK_PREFETCH_I 0x1f07fff +#define MATCH_PREFETCH_R 0x106013 +#define MASK_PREFETCH_R 0x1f07fff +#define MATCH_PREFETCH_W 0x306013 +#define MASK_PREFETCH_W 0x1f07fff /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 048ab0a5d6..5462b5ecea 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -388,6 +388,7 @@ enum riscv_insn_class INSN_CLASS_V, INSN_CLASS_ZVEF, INSN_CLASS_SVINVAL, + INSN_CLASS_ZICBOP, }; /* This structure holds information for a particular instruction. */ |