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authorTCWG BuildSlave <tcwg-buildslave@linaro.org>2023-11-03 11:03:27 +0000
committerTCWG BuildSlave <tcwg-buildslave@linaro.org>2023-11-03 11:03:27 +0000
commit3a356802ce49f815fe8b02286b9fef57ea769c42 (patch)
tree301e88203fba60438e33a8da3bf55d180b360067 /notify/mail-body.txt
parent0966215907d87e751b3c56d90a3747f71153184d (diff)
onsuccess: #99: all: [TCWG CI] https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-mainline-allyesconfig-build/99/
Results : | # reset_artifacts: | -10 | # build_abe binutils: | -9 | # build_kernel_llvm: | -5 | # build_abe qemu: | -2 | # linux_n_obj: | 22369 | # linux build successful: | all check_regression status : 0
Diffstat (limited to 'notify/mail-body.txt')
-rw-r--r--notify/mail-body.txt48
1 files changed, 21 insertions, 27 deletions
diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index ac39276..b67354a 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -2,31 +2,25 @@ Dear contributor, our automatic CI has detected problems related to your patch(e
In CI config tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig after:
- | 892 commits in binutils,llvm,linux,qemu
- | 2029e13917d RISC-V: Clarify the behaviors of SET/ADD/SUB relocations.
- | 1c47569f537 Automatic date update in version.in
- | ef8cf9093dc gdb/python: Add new gdb.Value.bytes attribute
- | fd492bf1e20 gdb: handle main thread exiting during detach
- | 743d3f0945c [gdb/testsuite] Add wait-for-index-cache in gdb.dwarf2/per-bfd-sharing.exp
- | ... and 29 more commits in binutils
- | fb619b3c78b1 [CMake] Address the issue introduced in #69869
- | 8e247b8f4734 Replace TypeSize::{getFixed,getScalable} with canonical TypeSize::{Fixed,Scalable}. NFC
- | 58d4fe287e02 [X86][EVEX512] Do not allow 512-bit memcpy without EVEX512 (#70420)
- | 7046202c3dde [flang] Move whole allocatable assignment implicit conversion to lowering (#70317)
- | fde1ecdec878 Revert "[libc++][tests] Fix a few remaining instances of outdated static assertion regexes in our test suite"
- | ... and 554 more commits in llvm
- | 750b95887e56 Merge tag 'drm-fixes-2023-10-27' of git://anongit.freedesktop.org/drm/drm
- | 44117828ed5c Merge tag 'amd-drm-fixes-6.6-2023-10-25' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
- | 5679dd241bbf Merge tag 'drm-intel-fixes-2023-10-26' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
- | 6366ffa6edd8 Merge tag 'drm-misc-fixes-2023-10-26' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes
- | 3a568e3a961b Merge tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
- | ... and 132 more commits in linux
- | a95260486a Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging
- | 1b4a5a20da Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
- | b093277edc Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
- | 338cf82fbe Merge tag 'hw-misc-20231020' of https://github.com/philmd/qemu into staging
- | e40df3522b target/xtensa: Use tcg_gen_sextract_i32
- | ... and 157 more commits in qemu
+ | 1156 commits in binutils,llvm,qemu
+ | c76820a017d RISC-V: reduce redundancy in load/store macro insn handling
+ | 0afb0215bdc RISC-V: Lx/Sx macro insn tests
+ | 3aacf044eb9 RISC-V: add F- and D-extension testcases
+ | e4bec45d366 RISC-V: make FLQ/FSQ macro-insns work
+ | 268109cad16 Automatic date update in version.in
+ | ... and 38 more commits in binutils
+ | e9db60c05e2f Reapply [clang-repl] [test] Make an XFAIL more precise (#70991)
+ | 060de415af33 Reapply [InstCombine] Simplify and/or of icmp eq with op replacement (#70335)
+ | 05d52a415b39 [analyzer][NFC] Add a test case to PR 70792 for Issue 59493 and 54533 (#71073)
+ | 8e2b3309a975 [Docs][LTO] Updated HowToSubmitABug.rst for LTO crashes (#68389)
+ | 33a60141b310 Revert D87067 "[llvm-symbolizer] Add back --use-symbol-table=true"
+ | ... and 721 more commits in llvm
+ | d762bf9793 Merge tag 'pull-target-arm-20231102' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
+ | 75b7b25d44 Merge tag 'migration-20231102-pull-request' of https://gitlab.com/juan.quintela/qemu into staging
+ | 1c98a821a2 tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG device
+ | 3b22376ba4 hw/arm: xlnx-versal-virt: Add AMD/Xilinx TRNG device
+ | 921923583f hw/misc: Introduce AMD/Xilix Versal TRNG device
+ | ... and 382 more commits in qemu
Results changed to
# reset_artifacts:
@@ -62,6 +56,6 @@ CI config tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig
-----------------8<--------------------------8<--------------------------8<--------------------------
The information below can be used to reproduce a debug environment:
-Current build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-mainline-allyesconfig-build/97/artifact/artifacts
-Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-mainline-allyesconfig-build/96/artifact/artifacts
+Current build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-mainline-allyesconfig-build/99/artifact/artifacts
+Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-mainline-allyesconfig-build/97/artifact/artifacts