diff options
| author | TCWG BuildSlave <tcwg-buildslave@linaro.org> | 2023-07-07 10:01:53 +0000 |
|---|---|---|
| committer | TCWG BuildSlave <tcwg-buildslave@linaro.org> | 2023-07-07 10:01:53 +0000 |
| commit | 062369f26bf9fdfd49986b5dfe4c996a44d85f15 (patch) | |
| tree | 431fe0fff03d9e796a895868e12a9543ffbaecf3 /notify/mail-body.txt | |
| parent | 7402cae3a891d871926ff92494cdbfe68792f633 (diff) | |
onsuccess: #54: 22015: [TCWG CI] https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-mainline-allyesconfig-build/54/
Results :
| # reset_artifacts:
| -10
| # build_abe binutils:
| -9
| # build_kernel_llvm:
| -5
| # build_abe qemu:
| -2
| # linux_n_obj:
| 22015
check_regression status : 0
Diffstat (limited to 'notify/mail-body.txt')
| -rw-r--r-- | notify/mail-body.txt | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/notify/mail-body.txt b/notify/mail-body.txt new file mode 100644 index 0000000..5c05089 --- /dev/null +++ b/notify/mail-body.txt @@ -0,0 +1,57 @@ +[TCWG-CI] Success after commit: 637 commits in binutils,llvm,qemu + +In CI config tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig after: + | binutils commits: + | 36b7610ad70d300fd4b76a3ac7a94ff56e23eb7f Automatic date update in version.in + | 31a56a22c45d76df4c597439f337e3f75ac3065c Linux: Avoid pread64/pwrite64 for high memory addresses (PR gdb/30525) + | c0c3bb70f2f13e07295041cdf24a4d2997fe99a4 riscv: Ensure LE instruction fetching + | b2ad7bb9e6a012699195d3eda9d40679c406ebdc Fix Solaris regression (PR tdep/30252) + | 0fa7d86440de0124efaf11ced82875d39a2296bc ld: fix plugin tests for MIPS PIC + | ... and 30 more + | llvm commits: + | 99074aafc31593c9935da483edab1333d6ce5a5b [bazel] Port for 88e95c1e4bb6e2ad3bfd185b96341ad5c09eff6b + | 2b5ea51a417fd4454128bd55bf3eb7e7719dee2a [compiler-rt][RISCV] Fix __fe_getround and __fe_raise_inexact for Zfinx + | c0221e006d47ed24c4562f264411943596a6800e [RISCV] Add a pass to combine `cm.pop` and `ret` insts + | a10dccf2712fe4c9d90684626f510913bc6d1307 [X86] Support some Intel CPUs for cpu_specific/dispatch feature + | 43927542d8364ae1c3838625c027f6fb31c3d3e6 [RISCV] Rename prefix `fixed-vector` to `fixed-vectors` to be the same with other testcases. NFC. + | ... and 538 more + | qemu commits: + | 97c81ef4b8e203d9620fd46e7eb77004563e3675 Merge tag 'pull-9p-20230706' of https://github.com/cschoenebeck/qemu into staging + | 822cb97cefe2416ce61fe8007ad69904bbe24502 Merge tag 'pull-target-arm-20230706' of https://git.linaro.org/people/pmaydell/qemu-arm into staging + | c41077235168140cdd4a34fce9bd95c3d30efe9c target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case + | c74138c6c040b62e941326a4fbb25a93fdd35b72 target/arm: Define neoverse-v1 + | 7d8c283e10dd818457e7c6a0f729fb03857253ac target/arm: Suppress more TCG unimplemented features in ID registers + | ... and 54 more + +Results changed to +# reset_artifacts: +-10 +# build_abe binutils: +-9 +# build_kernel_llvm: +-5 +# build_abe qemu: +-2 +# linux_n_obj: +22015 + +From +# reset_artifacts: +-10 +# build_abe binutils: +-9 +# build_kernel_llvm: +-5 +# build_abe qemu: +-2 +# linux_n_obj: +22015 + + + +-----------------8<--------------------------8<--------------------------8<-------------------------- +The information below can be used to reproduce a debug environment: + +Current build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-mainline-allyesconfig-build/54/artifact/artifacts +Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-mainline-allyesconfig-build/52/artifact/artifacts + |