diff options
Diffstat (limited to 'notify/mail-body.txt')
| -rw-r--r-- | notify/mail-body.txt | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/notify/mail-body.txt b/notify/mail-body.txt index 0602c32..5fda20f 100644 --- a/notify/mail-body.txt +++ b/notify/mail-body.txt @@ -2,25 +2,25 @@ Dear contributor, our automatic CI has detected problems related to your patch(e In CI config tcwg_kernel/gnu-master-arm-next-allmodconfig after: - | 131 commits in binutils,gcc,qemu - | 31477859c0c testsuite: Clean up .allow_index_reg in i386 tests - | 314f65803f1 testsuite: Clean up #as in dump file for i386 tests - | 9a20cccbcd8 Automatic date update in version.in - | 66637e209cc i386: Use a fallback XSAVE layout for remote targets - | f1b8ee6f2b4 [gdb/testsuite] Add boards/cc-with-index-cache.exp - | ... and 24 more commits in binutils - | ce52f1f7074 libcpp: Fix unsigned promotion for unevaluated divide by zero [PR112701] - | 9c16ca93641 RISC-V: Fix VSETVL PASS regression - | 5099525bff4 diagnostics: don't print annotation lines when there's no column info - | 93096d3ce14 diagnostics: add diagnostic_context::get_location_text - | ad3e759c172 Daily bump. - | ... and 82 more commits in gcc - | 4705fc0c85 Merge tag 'pull-for-8.2-fixes-231123-1' of https://gitlab.com/stsquad/qemu into staging - | 6ef164188d tests/tcg: finesse the registers check for "hidden" regs - | c2118e9e1a configure: don't try a "native" cross for linux-user - | 8848c52967 tests/tcg: enable semiconsole test for Arm - | 56611e17d2 tests/tcg: enable arm softmmu tests - | ... and 10 more commits in qemu + | 647 commits in binutils,gcc,qemu + | c64ec6d0825 sim: aarch64: fix -Wunused-but-set-variable warnings + | 3762437eadd sim: common: fix -Wunused-but-set-variable warnings + | 8958a917148 sim: ppc: fix -Wunused-but-set-variable warnings + | bbe7b93875b sim: v850: fix -Wunused-but-set-variable warnings + | 49b556efb55 sim: sh: fix -Wunused-but-set-variable warnings + | ... and 145 more commits in binutils + | 2efe3a7de01 tree-optimization/112774: extend the SCEV CHREC tree with a nonwrapping flag + | 9f7ad5eff3b [PATCH 1/5][V3][ifcvt] optimize x=c ? (y op z) : y by RISC-V Zicond like insns + | 775aeabcb87 analyzer: fix ICE for 2 bits before the start of base region [PR112889] + | 08f89e5e7f4 Daily bump. + | 71a5ac6703d RISC-V: Support interleave vector with different step sequence + | ... and 396 more commits in gcc + | 9c74490bff Update version for v8.2.0-rc3 release + | 5746f70d68 i386/sev: Avoid SEV-ES crash due to missing MSR_EFER_LMA bit + | d451e32ce8 Merge tag 'pull-ufs-20231205' of https://gitlab.com/jeuk20.kim/qemu into staging + | 80a37b039e hw/ufs: avoid generating the same ID string for different LU devices + | eeaaf96f55 Merge tag 'misc-fixes-20231204' of https://github.com/philmd/qemu into staging + | ... and 91 more commits in qemu Results changed to # reset_artifacts: @@ -60,6 +60,6 @@ CI config tcwg_kernel/gnu-master-arm-next-allmodconfig -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: -Current build : https://ci.linaro.org/job/tcwg_kernel--gnu-master-arm-next-allmodconfig-build/86/artifact/artifacts -Reference build : https://ci.linaro.org/job/tcwg_kernel--gnu-master-arm-next-allmodconfig-build/85/artifact/artifacts +Current build : https://ci.linaro.org/job/tcwg_kernel--gnu-master-arm-next-allmodconfig-build/90/artifact/artifacts +Reference build : https://ci.linaro.org/job/tcwg_kernel--gnu-master-arm-next-allmodconfig-build/86/artifact/artifacts |