onsuccess: #312: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_ubsan-build/312/

Results :
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap_ubsan:
  | 1

check_regression status : 0

4 files changed, 12 insertions, 12 deletions

diff --git a/notify/jira/comment-template.txt b/notify/jira/comment-template.txt
index f1db850..977d4da 100644
--- a/notify/jira/comment-template.txt
+++ b/notify/jira/comment-template.txt
@@ -1,3 +1,3 @@
 [GNU-692]
 Success
-Details: https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_ubsan-build/311/artifact/artifacts/notify/mail-body.txt/*view*/
+Details: https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_ubsan-build/312/artifact/artifacts/notify/mail-body.txt/*view*/
diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index 3b20bf2..b0681fa 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -4,13 +4,13 @@ We appreciate that it might be difficult to find the necessary logs or reproduce
 
 In bootstrap_build master-aarch64-bootstrap_ubsan after:
 
-  | 13 commits in gcc
-  | ed60b2868ab RISC-V: Move RVV V_REGS liveness computation into analyze_loop_vinfo
-  | fd032cce216 middle-end: explicitly initialize vec_stmts [PR113132]
-  | 1bbb169fe6f rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320]
-  | 0beeddd6b1b RISC-V: Add one more ASM check in PR113112-1.c
-  | 59ecd5ff096 match: Improve `(a != b) ? (a + b) : (2 * a)` pattern [PR19832]
-  | ... and 8 more commits in gcc
+  | 6 commits in gcc
+  | 87dfd707233 RISC-V: Fix typo
+  | f83cfb8148b RISC-V: Some minior tweak on dynamic LMUL cost model
+  | 6cec7b06b3c Fix compile options of pr110279-1.c and pr110279-2.c
+  | 7c6615692e0 testsuite: Add dg-require-effective-target powerpc_pcrel for testcase [PR110320]
+  | 07ee6d7b2c3 Daily bump.
+  | ... and 1 more commits in gcc
 
 Results changed to
 # reset_artifacts:
@@ -34,6 +34,6 @@ CI config tcwg_bootstrap_build master-aarch64-bootstrap_ubsan
 -----------------8<--------------------------8<--------------------------8<--------------------------
 The information below can be used to reproduce a debug environment:
 
-Current build   : https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_ubsan-build/311/artifact/artifacts
-Reference build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_ubsan-build/310/artifact/artifacts
+Current build   : https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_ubsan-build/312/artifact/artifacts
+Reference build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_ubsan-build/311/artifact/artifacts
 
diff --git a/notify/mail-recipients.txt b/notify/mail-recipients.txt
index 606be45..a97731b 100644
--- a/notify/mail-recipients.txt
+++ b/notify/mail-recipients.txt
@@ -1 +1 @@
-bcc:tcwg-validation@linaro.org,danglin@gcc.gnu.org,cc:gcc-regression@gcc.gnu.org,tamar.christina@arm.com,cc:juzhe.zhong@rivai.ai,gccadmin@gcc.gnu.org,pan2.li@intel.com,jeevitha@linux.ibm.com,quic_apinski@quicinc.com
+dje.gcc@gmail.com,bcc:tcwg-validation@linaro.org,cc:gcc-regression@gcc.gnu.org,cc:juzhe.zhong@rivai.ai,dizhao@os.amperecomputing.com,gccadmin@gcc.gnu.org,pan2.li@intel.com,jeevitha@linux.ibm.com
diff --git a/notify/mail-subject.txt b/notify/mail-subject.txt
index 8b54b6b..b2d0dc6 100644
--- a/notify/mail-subject.txt
+++ b/notify/mail-subject.txt
@@ -1 +1 @@
-[Linaro-TCWG-CI] 13 commits in gcc: Success on aarch64
+[Linaro-TCWG-CI] 6 commits in gcc: Success on aarch64