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Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain@lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel.
In CI config tcwg_bmk-qc_speed-cpu2017rate/llvm-aarch64-master-O3_LTO after:
| 122 commits in llvm
| 7e0bae5b3433 [RISCV][GISel] Add isel patterns for SHXADD with s32 type on RV64.
| a93dfb589d17 [RISCV] Peek through zext in selectShiftMask.
| 83cc24e598b7 [RISCV] Add test case showing unnecessary zext of shift amounts with -riscv-experimental-rv64-legal-i32. NFC
| 309596f24977 [LLDB] Ensure the data of apple accelerator tables is kept around (#71828)
| 00c3c731893c [mlir][gpu] Separate the barrier elimination code from transform ops (#71762)
| ... and 117 more commits in llvm
No change
The configuration of this build is:
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI.
Configuration:
- Benchmark: SPEC CPU2017
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: O3 -LTO
- Hardware: Qualcomm 8x AA64
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain@lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
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The information below can be used to reproduce a debug environment:
Current build : https://ci.linaro.org/job/tcwg_bmk-qc_speed-cpu2017rate--llvm-aarch64-master-O3_LTO-build/92/artifact/artifacts
Reference build : https://ci.linaro.org/job/tcwg_bmk-qc_speed-cpu2017rate--llvm-aarch64-master-O3_LTO-build/91/artifact/artifacts
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