diff options
| author | TCWG BuildSlave <tcwg-buildslave@linaro.org> | 2023-11-13 06:57:09 +0000 |
|---|---|---|
| committer | TCWG BuildSlave <tcwg-buildslave@linaro.org> | 2023-11-13 06:58:03 +0000 |
| commit | e6a9e96ef2d8154855c3ebb4732a599cf80eed8d (patch) | |
| tree | 45e00997248eaadb9669838583310b51f33e885d /notify/mail-body.txt | |
| parent | b5753f556f647747df4d731633546b65e3650363 (diff) | |
onsuccess: #84: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_bmk-code_vect-cpu2017rate--llvm-arm-master-O3_LTO-build/84/
Results :
| # reset_artifacts:
| -10
| # build_bmk_llvm:
| -3
| # benchmark -- -O3_LTO_marm:
| 1
check_regression status : 0
Diffstat (limited to 'notify/mail-body.txt')
| -rw-r--r-- | notify/mail-body.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/notify/mail-body.txt b/notify/mail-body.txt index f1d2a6d..0be96e4 100644 --- a/notify/mail-body.txt +++ b/notify/mail-body.txt @@ -2,13 +2,13 @@ Dear contributor, our automatic CI has detected problems related to your patch(e In CI config tcwg_bmk-code_vect-cpu2017rate/llvm-arm-master-O3_LTO after: - | 352 commits in llvm - | fdbff88196b5 [RISCV][GISel] Add support for G_FCMP with F and D extensions. (#70624) - | aae30f9e2c25 [RISCV] Use Align(8) for the stack temporary created for SPLAT_VECTOR_SPLIT_I64_VL. - | 63251f49cf88 [RISCV][GISel] Add regbank select for G_INVOKE_REGION_START. - | 0e7b30fa821d [C++20] [Modules] Enhance better diagnostic for implicit global module and module partitions - | dc3faf0ed0e3 ValueTracking: Identify implied fp classes by general fcmp (#66505) - | ... and 347 more commits in llvm + | 211 commits in llvm + | 89ecb8001afc MapVector: add C++17-style try_emplace and insert_or_assign (#71969) + | 868007a03c74 [clang][Sema] Avoid non-empty unexpanded pack assertion for FunctionParmPackExpr (#69224) + | 285a229f205a [MLIR] Apply clang-tidy fixes for misc-include-cleaner (NFC) + | 44e8bea4009a [GISel][AArch64] Notify the Observer when CTTZ lowering changes the opcode to CTPOP. (#72008) + | ec4a03c65884 [BOLT] Enhance LowerAnnotations pass. NFCI. (#71847) + | ... and 206 more commits in llvm No change @@ -28,6 +28,6 @@ This benchmarking CI is work-in-progress, and we welcome feedback and suggestion -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: -Current build : https://ci.linaro.org/job/tcwg_bmk-code_vect-cpu2017rate--llvm-arm-master-O3_LTO-build/83/artifact/artifacts -Reference build : https://ci.linaro.org/job/tcwg_bmk-code_vect-cpu2017rate--llvm-arm-master-O3_LTO-build/82/artifact/artifacts +Current build : https://ci.linaro.org/job/tcwg_bmk-code_vect-cpu2017rate--llvm-arm-master-O3_LTO-build/84/artifact/artifacts +Reference build : https://ci.linaro.org/job/tcwg_bmk-code_vect-cpu2017rate--llvm-arm-master-O3_LTO-build/83/artifact/artifacts |