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Diffstat (limited to 'notify/jira/description')
| -rw-r--r-- | notify/jira/description | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/notify/jira/description b/notify/jira/description new file mode 100644 index 0000000..c83b31a --- /dev/null +++ b/notify/jira/description @@ -0,0 +1,25 @@ +Commit: https://github.com/llvm/llvm-project/commit/147c5d6686b935ecd93f8fa0e2dcf38deb593890 +commit llvmorg-18-init-12505-g147c5d6686b9 +Author: Zhaoxuan Jiang <jiangzhaoxuan94@gmail.com> +Date: Thu Nov 23 16:21:27 2023 +0800 + + [AArch64] Allow LDR merge with same destination register by renaming (#71908) + + The patch is based on a reverted patch: + https://reviews.llvm.org/D103597. It was trying to rename registers + before alias check, which is not safe and causes miscompiles. This patch + does 2 things: + +... 8 lines of the commit log omitted. + +* tcwg_bmk-code_speed-cpu2017rate +** llvm-aarch64-master-O3 +*** slowed down by 7% - 549.fotonik3d_r +*** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/147c5d6686b935ecd93f8fa0e2dcf38deb593890/tcwg_bmk-code_speed-cpu2017rate/llvm-aarch64-master-O3/details.txt +*** https://ci.linaro.org/job/tcwg_bmk-code_speed-cpu2017rate--llvm-aarch64-master-O3-build/145/ +** llvm-arm-master-O3 +*** slowed down by 100% - 508.namd_r:libc.so.6 +*** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/147c5d6686b935ecd93f8fa0e2dcf38deb593890/tcwg_bmk-code_speed-cpu2017rate/llvm-arm-master-O3/details.txt +*** https://ci.linaro.org/job/tcwg_bmk-code_speed-cpu2017rate--llvm-arm-master-O3-build/104/ + +Latest data: https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/147c5d6686b935ecd93f8fa0e2dcf38deb593890/jira/yaml |