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- Project: LLVM
IssueType: Sub-task
Key: LLVM-928
Summary: |
llvmorg-18-init-5853-gcbdccb30c23f: 511.povray_r:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
Components: LLVM
Start date: 2023-09-15
Description: |
commit llvmorg-18-init-5853-gcbdccb30c23f
Author: Guozhi Wei <carrot@google.com>
Date: Fri Sep 15 19:52:50 2023 +0000
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
If a virtual register is not assigned preferred physical register, it means some
COPY instructions will be changed to real register move instructions. In this
case we can try to split the virtual register in colder blocks, if success, the
original COPY instructions can be deleted, and the new COPY instructions in
colder blocks will be generated as register move instructions. It results in
... 7 lines of the commit log omitted.
* tcwg_bmk-code_size-cpu2017fast
** llvm-aarch64-master-O3
*** 511.povray_r:[.] _ZN3povL24All_Sphere_IntersectionsEPNS_13Object_StructEPNS_10Ray_StructEPNS_13istack_structE grew in size by 12%
*** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_size-cpu2017fast/llvm-aarch64-master-O3/details.txt
*** https://ci.linaro.org/job/tcwg_bmk-code_size-cpu2017fast--llvm-aarch64-master-O3-build/71/
* tcwg_bmk-code_speed-cpu2017rate
** llvm-aarch64-master-O3
*** 526.blender_r slowed down by 4%
*** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/tcwg_bmk-code_speed-cpu2017rate/llvm-aarch64-master-O3/details.txt
*** https://ci.linaro.org/job/tcwg_bmk-code_speed-cpu2017rate--llvm-aarch64-master-O3-build/98/
Latest data: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/llvm/sha1/cbdccb30c23f71f20d05b19256232419e7c5e517/jira/yaml
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