diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2013-02-18 16:58:34 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-05-03 23:07:46 +0100 |
| commit | aa10ed3b6f71fec9b60708233d5bec043aa9f35a (patch) | |
| tree | db78e8f01a4ab87a2a97c070d208f2db2943bea5 | |
| parent | bb4a74c0981d914c41d5df51f625d0148d47ce1e (diff) | |
hw/nand: Support cache status bits and read cache commands
TODO: check vs spec, are we just ignoring these commands, is
that correct?
consider renaming the ready bits
On reset, set the Ready bits in the status register (both the
original bit 6 and the new bit 5 used by eg the STM NAND chips).
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
[Riku Voipio: Fixes and restructuring patchset]
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
[Peter Maydell: More fixes and cleanups for upstream submission]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/block/nand.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/hw/block/nand.c b/hw/block/nand.c index 61d2cec03..3f4ed390c 100644 --- a/hw/block/nand.c +++ b/hw/block/nand.c @@ -28,6 +28,9 @@ # define NAND_CMD_READ1 0x01 # define NAND_CMD_READ2 0x50 # define NAND_CMD_LPREAD2 0x30 +# define NAND_CMD_READCACHESTART 0x31 +# define NAND_CMD_READCACHEEXIT 0x34 +# define NAND_CMD_READCACHELAST 0x3f # define NAND_CMD_NOSERIALREAD2 0x35 # define NAND_CMD_RANDOMREAD1 0x05 # define NAND_CMD_RANDOMREAD2 0xe0 @@ -46,7 +49,7 @@ # define NAND_IOSTATUS_PLANE1 (1 << 2) # define NAND_IOSTATUS_PLANE2 (1 << 3) # define NAND_IOSTATUS_PLANE3 (1 << 4) -# define NAND_IOSTATUS_READY (1 << 6) +# define NAND_IOSTATUS_READY (3 << 5) # define NAND_IOSTATUS_UNPROTCT (1 << 7) # define MAX_PAGE 0x800 @@ -253,6 +256,7 @@ static void nand_command(NANDFlashState *s) unsigned int offset; switch (s->cmd) { case NAND_CMD_READ0: + case NAND_CMD_READCACHEEXIT: s->iolen = 0; break; @@ -485,7 +489,10 @@ void nand_setio(DeviceState *dev, uint32_t value) if (!s->ce && s->cle) { if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) { - if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2) + if (s->cmd == NAND_CMD_READ0 + && (value == NAND_CMD_LPREAD2 + || value == NAND_CMD_READCACHESTART + || value == NAND_CMD_READCACHELAST)) return; if (value == NAND_CMD_RANDOMREAD1) { s->addr &= ~((1 << s->addr_shift) - 1); @@ -511,7 +518,8 @@ void nand_setio(DeviceState *dev, uint32_t value) s->cmd == NAND_CMD_BLOCKERASE2 || s->cmd == NAND_CMD_NOSERIALREAD2 || s->cmd == NAND_CMD_RANDOMREAD2 || - s->cmd == NAND_CMD_RESET) { + s->cmd == NAND_CMD_RESET || + s->cmd == NAND_CMD_READCACHEEXIT) { nand_command(s); } |