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authorPeter Maydell <peter.maydell@linaro.org>2013-02-18 16:58:27 +0000
committerPeter Maydell <peter.maydell@linaro.org>2015-05-03 21:22:21 +0100
commit6d0b1955d9b15dc41ffe2be796fbd355a6b92d43 (patch)
treea2b9fe6c348982d44c9fa4c607b762198d4d756a
parent07dc92f9dc0e3b53c52643ffbdd6e9862dfc6e17 (diff)
hw/omap_i2c: Treat 32 bit accesses like 16 bit accesses
Treat 32 bit OMAP i2c register accesses like 16 bit accesses, working around the kernel bug LP:727781 where it makes 32 bit accesses in violation of the TRM. (Hardware behaviour is apparently that OMAP2 will abort on these 32 bit accesses, but OMAP3 and 4 will allow them.) We might need to revert or rethink this patch as part of handling silencing of bad-kernel-behaviour warnings more consistently so that they can be upstreamed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/i2c/omap_i2c.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c
index 015b0fd16..d5dbf9f1d 100644
--- a/hw/i2c/omap_i2c.c
+++ b/hw/i2c/omap_i2c.c
@@ -653,12 +653,12 @@ static const MemoryRegionOps omap_i2c_ops = {
.read = {
omap_i2c_readb,
omap_i2c_read,
- omap_badwidth_read16,
+ omap_i2c_read,
},
.write = {
omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
omap_i2c_write,
- omap_badwidth_write16,
+ omap_i2c_write,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,