From 1fb4dc5c39af941d3abc597337e0ea776bfce0f2 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 27 Feb 2013 21:54:51 +0000 Subject: metag: perf: don't reset TXTACTCYC The thread active cycle counter TXTACTCYC is used in __delay so it shouldn't really be reset to zero by perf. Fix perf to just read the value, and instead of clearing it, record the prev_count value in enable_counter so that the delta calculations know about the previous value. Signed-off-by: James Hogan Cc: Peter Zijlstra Cc: Paul Mackerras Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo --- arch/metag/kernel/perf/perf_event.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'arch/metag') diff --git a/arch/metag/kernel/perf/perf_event.c b/arch/metag/kernel/perf/perf_event.c index 54fde35b4b9..a1eff3687e8 100644 --- a/arch/metag/kernel/perf/perf_event.c +++ b/arch/metag/kernel/perf/perf_event.c @@ -617,9 +617,7 @@ static void metag_pmu_enable_counter(struct hw_perf_event *event, int idx) WARN_ONCE((config != 0x100), "invalid configuration (%d) for counter (%d)\n", config, idx); - - /* Reset the cycle count */ - __core_reg_set(TXTACTCYC, 0); + local64_set(&event->prev_count, __core_reg_get(TXTACTCYC)); goto unlock; } @@ -708,9 +706,8 @@ static u64 metag_pmu_read_counter(int idx) { u32 tmp = 0; - /* The act of reading the cycle counter also clears it */ if (METAG_INST_COUNTER == idx) { - __core_reg_swap(TXTACTCYC, tmp); + tmp = __core_reg_get(TXTACTCYC); goto out; } -- cgit v1.2.3