1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
|
/*
* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <cpu_macros.S>
#include <qemu_max.h>
func qemu_max_core_pwr_dwn
/* ---------------------------------------------
* Disable the Data Cache.
* ---------------------------------------------
*/
mrs x1, sctlr_el3
bic x1, x1, #SCTLR_C_BIT
msr sctlr_el3, x1
isb
/* ---------------------------------------------
* Flush L1 cache to L2.
* ---------------------------------------------
*/
mov x18, lr
mov x0, #DCCISW
bl dcsw_op_level1
mov lr, x18
ret
endfunc qemu_max_core_pwr_dwn
func qemu_max_cluster_pwr_dwn
/* ---------------------------------------------
* Disable the Data Cache.
* ---------------------------------------------
*/
mrs x1, sctlr_el3
bic x1, x1, #SCTLR_C_BIT
msr sctlr_el3, x1
isb
/* ---------------------------------------------
* Flush all caches to PoC.
* ---------------------------------------------
*/
mov x0, #DCCISW
b dcsw_op_all
endfunc qemu_max_cluster_pwr_dwn
errata_report_shim qemu_max
/* ---------------------------------------------
* This function provides cpu specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
* x8 - x15 having values of registers to be
* reported.
* ---------------------------------------------
*/
.section .rodata.qemu_max_regs, "aS"
qemu_max_regs: /* The ascii list of register names to be reported */
.asciz "" /* no registers to report */
func qemu_max_cpu_reg_dump
adr x6, qemu_max_regs
ret
endfunc qemu_max_cpu_reg_dump
/* cpu_ops for QEMU MAX */
declare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \
qemu_max_core_pwr_dwn, \
qemu_max_cluster_pwr_dwn
|
