From c1e84aca3831c8a768b862061ab95b22168c0564 Mon Sep 17 00:00:00 2001 From: Prasad Kummari Date: Wed, 4 Oct 2023 10:20:30 +0530 Subject: refactor(xilinx): create generic function for clock retrieval Refactors the code in the AMD-Xilinx platform for Versal and Versal NET to create a more generic function for obtaining clock signals from the platform. The new function get_uart_clk is specific to each platform and providing greater flexibility for clock signal retrieval in various parts of the codebase. Signed-off-by: Prasad Kummari Change-Id: Iff67315339b2651c9bea73af0d89fcbad2bb332a --- plat/xilinx/versal/aarch64/versal_common.c | 5 +++++ plat/xilinx/versal/bl31_versal_setup.c | 3 ++- plat/xilinx/versal/include/plat_private.h | 1 + plat/xilinx/versal_net/aarch64/versal_net_common.c | 24 ++++++++++++++++++++++ plat/xilinx/versal_net/bl31_versal_net_setup.c | 8 ++------ plat/xilinx/versal_net/include/plat_private.h | 1 + 6 files changed, 35 insertions(+), 7 deletions(-) (limited to 'plat') diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c index 93deedc63..6541f2734 100644 --- a/plat/xilinx/versal/aarch64/versal_common.c +++ b/plat/xilinx/versal/aarch64/versal_common.c @@ -73,3 +73,8 @@ void board_detection(void) platform_id = FIELD_GET(PLATFORM_MASK, plat_info[1]); platform_version = FIELD_GET(PLATFORM_VERSION_MASK, plat_info[1]); } + +uint32_t get_uart_clk(void) +{ + return UART_CLOCK; +} diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c index 566415f16..8106db805 100644 --- a/plat/xilinx/versal/bl31_versal_setup.c +++ b/plat/xilinx/versal/bl31_versal_setup.c @@ -73,12 +73,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; enum pm_ret_status ret_status; uint64_t addr[HANDOFF_PARAMS_MAX_SIZE]; + uint32_t uart_clk = get_uart_clk(); if (CONSOLE_IS(pl011) || (CONSOLE_IS(pl011_1))) { static console_t versal_runtime_console; /* Initialize the console to provide early debug support */ int32_t rc = console_pl011_register((uintptr_t)UART_BASE, - (uint32_t)UART_CLOCK, + uart_clk, (uint32_t)UART_BAUDRATE, &versal_runtime_console); if (rc == 0) { diff --git a/plat/xilinx/versal/include/plat_private.h b/plat/xilinx/versal/include/plat_private.h index 48f64eaf9..26545ba0f 100644 --- a/plat/xilinx/versal/include/plat_private.h +++ b/plat/xilinx/versal/include/plat_private.h @@ -17,6 +17,7 @@ typedef struct versal_intr_info_type_el3 { interrupt_type_handler_t handler; } versal_intr_info_type_el3_t; +uint32_t get_uart_clk(void); void versal_config_setup(void); const mmap_region_t *plat_versal_get_mmap(void); diff --git a/plat/xilinx/versal_net/aarch64/versal_net_common.c b/plat/xilinx/versal_net/aarch64/versal_net_common.c index b2de411fe..df18814fb 100644 --- a/plat/xilinx/versal_net/aarch64/versal_net_common.c +++ b/plat/xilinx/versal_net/aarch64/versal_net_common.c @@ -88,6 +88,30 @@ void board_detection(void) platform_version / 10U, platform_version % 10U); } +uint32_t get_uart_clk(void) +{ + uint32_t uart_clock; + + switch (platform_id) { + case VERSAL_NET_SPP: + uart_clock = 1000000; + break; + case VERSAL_NET_EMU: + uart_clock = 25000000; + break; + case VERSAL_NET_QEMU: + uart_clock = 25000000; + break; + case VERSAL_NET_SILICON: + uart_clock = 100000000; + break; + default: + panic(); + } + + return uart_clock; +} + void versal_net_config_setup(void) { uint32_t val; diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c index a70095d40..7e877a4a5 100644 --- a/plat/xilinx/versal_net/bl31_versal_net_setup.c +++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c @@ -69,33 +69,29 @@ static inline void bl31_set_default_config(void) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - uint32_t uart_clock; int32_t rc; #if !(TFA_NO_PM) uint64_t tfa_handoff_addr, buff[HANDOFF_PARAMS_MAX_SIZE] = {0}; uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; enum pm_ret_status ret_status; #endif /* !(TFA_NO_PM) */ + uint32_t uart_clk = get_uart_clk(); board_detection(); switch (platform_id) { case VERSAL_NET_SPP: cpu_clock = 1000000; - uart_clock = 1000000; break; case VERSAL_NET_EMU: cpu_clock = 3660000; - uart_clock = 25000000; break; case VERSAL_NET_QEMU: /* Random values now */ cpu_clock = 100000000; - uart_clock = 25000000; break; case VERSAL_NET_SILICON: cpu_clock = 100000000; - uart_clock = 100000000; break; default: panic(); @@ -105,7 +101,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, static console_t versal_net_runtime_console; /* Initialize the console to provide early debug support */ - rc = console_pl011_register(UART_BASE, uart_clock, + rc = console_pl011_register(UART_BASE, uart_clk, UART_BAUDRATE, &versal_net_runtime_console); if (rc == 0) { diff --git a/plat/xilinx/versal_net/include/plat_private.h b/plat/xilinx/versal_net/include/plat_private.h index be75bfdfa..3eb80525e 100644 --- a/plat/xilinx/versal_net/include/plat_private.h +++ b/plat/xilinx/versal_net/include/plat_private.h @@ -18,6 +18,7 @@ typedef struct versal_intr_info_type_el3 { } versal_intr_info_type_el3_t; void versal_net_config_setup(void); +uint32_t get_uart_clk(void); const mmap_region_t *plat_versal_net_get_mmap(void); -- cgit v1.2.3