From d3331603664ca7d4ab1510df09e722e6ffb1df29 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 14 Mar 2023 20:13:03 +0000 Subject: feat(tcr2): support FEAT_TCR2 Arm v8.9 introduces FEAT_TCR2, adding extended translation control registers. Support this, context switching TCR2_EL2 and disabling traps so lower ELs can access the new registers. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown Change-Id: I297452acd8646d58bac64fc15e05b06a543e5148 --- lib/el3_runtime/aarch64/context_mgmt.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'lib/el3_runtime') diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 4d2079d23..507a8ce8a 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -347,6 +347,13 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e scr_el3 |= SCR_FIEN_BIT; #endif + /* + * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. + */ + if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { + scr_el3 |= SCR_TCR2EN_BIT; + } + /* * CPTR_EL3 was initialized out of reset, copy that value to the * context register. @@ -884,6 +891,9 @@ void cm_el2_sysregs_context_save(uint32_t security_state) if (is_feat_hcx_supported()) { write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); } + if (is_feat_tcr2_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); + } } } @@ -944,6 +954,9 @@ void cm_el2_sysregs_context_restore(uint32_t security_state) if (is_feat_hcx_supported()) { write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); } + if (is_feat_tcr2_supported()) { + write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); + } } } #endif /* CTX_INCLUDE_EL2_REGS */ -- cgit v1.2.3