From 9202d51990c192e8bc041e6f53d5ce63ee908665 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Mon, 13 Feb 2023 12:39:17 +0000 Subject: refactor(ras): replace RAS_EXTENSION with FEAT_RAS The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec --- lib/el3_runtime/aarch64/context.S | 12 ++++++------ lib/el3_runtime/aarch64/context_mgmt.c | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'lib/el3_runtime') diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 769117163..63566da06 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -17,10 +17,10 @@ .global el2_sysregs_context_save_mte .global el2_sysregs_context_restore_mte #endif /* CTX_INCLUDE_MTE_REGS */ -#if RAS_EXTENSION +#if ENABLE_FEAT_RAS .global el2_sysregs_context_save_ras .global el2_sysregs_context_restore_ras -#endif /* RAS_EXTENSION */ +#endif /* ENABLE_FEAT_RAS */ #endif /* CTX_INCLUDE_EL2_REGS */ .global el1_sysregs_context_save @@ -210,7 +210,7 @@ func el2_sysregs_context_restore_mte endfunc el2_sysregs_context_restore_mte #endif /* CTX_INCLUDE_MTE_REGS */ -#if RAS_EXTENSION +#if ENABLE_FEAT_RAS func el2_sysregs_context_save_ras /* * VDISR_EL2 and VSESR_EL2 registers are saved only when @@ -232,7 +232,7 @@ func el2_sysregs_context_restore_ras msr vsesr_el2, x12 ret endfunc el2_sysregs_context_restore_ras -#endif /* RAS_EXTENSION */ +#endif /* ENABLE_FEAT_RAS */ #endif /* CTX_INCLUDE_EL2_REGS */ @@ -855,7 +855,7 @@ sve_not_enabled: 1: #endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */ -#if IMAGE_BL31 && RAS_EXTENSION +#if IMAGE_BL31 && ENABLE_FEAT_RAS /* ---------------------------------------------------------- * Issue Error Synchronization Barrier to synchronize SErrors * before exiting EL3. We're running with EAs unmasked, so @@ -866,7 +866,7 @@ sve_not_enabled: esb #else dsb sy -#endif /* IMAGE_BL31 && RAS_EXTENSION */ +#endif /* IMAGE_BL31 && ENABLE_FEAT_RAS */ /* ---------------------------------------------------------- * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index e38b34dcd..3ddf5fa2f 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1012,7 +1012,7 @@ void cm_el2_sysregs_context_save(uint32_t security_state) write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, read_ttbr1_el2()); } -#if RAS_EXTENSION +#if ENABLE_FEAT_RAS el2_sysregs_context_save_ras(el2_sysregs_ctx); #endif @@ -1095,7 +1095,7 @@ void cm_el2_sysregs_context_restore(uint32_t security_state) write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); } -#if RAS_EXTENSION +#if ENABLE_FEAT_RAS el2_sysregs_context_restore_ras(el2_sysregs_ctx); #endif -- cgit v1.2.3