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2023-11-02fix(cpus): workaround for Cortex-X2 erratum 2742423Bipin Ravi
Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all revisions <= r2p1 and is still open. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775100/latest Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-11-02fix(cpus): workaround for Cortex-A710 erratum 2742423Bipin Ravi
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all revisions <= r2p1 and is still open. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-11-02fix(cpus): workaround for Neoverse N2 erratum 2340933Bipin Ravi
Neoverse N2 erratum 2340933 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR5_EL1[61] to 1. SDEN documentation: https://developer.arm.com/documentation/SDEN-1982442/latest Change-Id: I121add0dd35072c53392d33f049d893a5ff6354f Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-11-02fix(cpus): workaround for Neoverse N2 erratum 2346952Bipin Ravi
Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all revisions <= r0p2 and is fixed in r0p3. The workaround is to set L2 TQ size statically to it's full size. SDEN documentation: https://developer.arm.com/documentation/SDEN-1982442/latest Change-Id: I03c3cf1f951fbc906fdebcb99a523c5ac8ba055d Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-10-26Merge changes from topic "sm/err_errata" into integrationLauren Wehrmeister
* changes: fix(cpus): fix the rev-var of Neoverse-V1 fix(errata-abi): update the Neoverse-N2 errata ABI struct fix(errata-abi): update the neoverse-N1 errata ABI struct fix(cpus): fix the rev-var of Cortex-X2 fix(errata-abi): update the Cortex-A78C errata ABI struct fix(cpus): update the rev-var for Cortex-A78AE fix(errata-abi): update the Cortex-A76 errata ABI struct fix(cpus): fix the rev-var for Cortex-A710
2023-10-24fix(cpus): workaround for Cortex-A510 erratum 2080326Sona Mathew
Cortex-A510 erratum 2080326 is a Cat B erratum that applies to all revisions <= r0p2 and is fixed in r0p3. The workaround sequence helps perform a DSB after each TLBI instruction and can be applied only for version r0p2 and has minimal performance impact. The workaround is not applicable for versions < r0p2. SDEN documentation: https://developer.arm.com/documentation/SDEN1873361/latest Change-Id: Ib9bce8b711c25a79f7b2f891ae6f8b366fc80ddd Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): fix the rev-var of Neoverse-V1Sona Mathew
Update the revision and variant information in the errata ABI file, neoverse_v1.S file for erratum ID - 2294912 to match the revision and variant in the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1401781/latest Change-Id: I38a0f53c3515860ba442b5c0872c8ab051fdda6f Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(errata-abi): update the Neoverse-N2 errata ABI structSona Mathew
Updated the structure for Neoverse_N2 in the errata ABI file for the missing entries from the neoverse_n2.S file. Change-Id: I635c39014a7b3e842a978a59e122d508d4bcf3c1 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(errata-abi): update the neoverse-N1 errata ABI structSona Mathew
Updated the structure for Neoverse_N1 in the errata ABI file for the missing entries from the neoverse_n1.S file. Change-Id: I79a1a72b807781d65a6afc9e0367e77b21eecf41 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): fix the rev-var of Cortex-X2Sona Mathew
Update the revision and variant information in the errata ABI file, cortex_X2.S file for erratum ID - 2058056 to match the revision and variant in the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775100/latest Change-Id: I28ee39949d977c53d6f5243100f0c29bc3c0428c Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(errata-abi): update the Cortex-A78C errata ABI structSona Mathew
Updated the structure for Cortex-A78C in the errata ABI file for missing entries from the cortex_a78c.S file. Change-Id: I3d994337221de03264be235f1727de7494ed4312 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): update the rev-var for Cortex-A78AESona Mathew
Update the revision and variant information in the cortex_a78_ae.s and errata ABI file for erratum ID - 2376748 based on the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1707912/latest Change-Id: I082aac41adf717b0d5d59046a8933a3f5a3de94f Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(errata-abi): update the Cortex-A76 errata ABI structSona Mathew
Updated the structure for Cortex-A76 in the errata ABI file for the missing entries from the cortex_a76.S file. Change-Id: Iceaf26fb2de493a877c4c100c0137f9255fc8b9f Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): fix the rev-var for Cortex-A710Sona Mathew
Update the revision and variant information in the errata ABI file, cortex_A710.S file for erratum ID - 2058056 and erratum ID - 2055002 to match the revision and variant in the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest Change-Id: Ie010dae90dabf8670f588a06f9a606cf41e22afa Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-04fix(cpus): workaround for Cortex-X3 erratum 2070301Sona Mathew
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all revisions <= r1p2 and is still open. The workaround is to write the value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher in the most conservative mode instead of disabling it. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-09-22Merge "fix(errata-abi): fix the rev-var for Cortex-A710" into integrationBipin Ravi
2023-09-22Merge changes from topic "errata" into integrationLauren Wehrmeister
* changes: fix(cpus): workaround for Neoverse V2 erratum 2743011 fix(cpus): workaround for Neoverse V2 erratum 2779510 fix(cpus): workaround for Neoverse V2 erratum 2719105 fix(cpus): workaround for Neoverse V2 erratum 2331132
2023-09-21fix(errata-abi): fix the rev-var for Cortex-A710Sona Mathew
Update the revision and variant information in the errata ABI file for Cortex-A710, erratum ID - 2058056 to match the revision and variant in the cortex_a710.S file. Change-Id: I4b974ac1f94d770f3ae7c15c88f42380c944eb43 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2743011Bipin Ravi
Neoverse V2 erratum 2743011 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I0e06ca723a1cce51fb027b7160f3dd06a4c93e64
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2779510Bipin Ravi
Neoverse V2 erratum 2779510 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The workaround is to set bit[47] of CPUACTLR3_EL1 which might have a small impact on power and negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I6d937747bdcbf2913a64c4037f99918cbc466e80
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2719105Bipin Ravi
Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2331132Bipin Ravi
Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all revisions <= r0p2 and is still open. The workaround is to write the value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register which will place the data prefetcher in the most conservative mode instead of disabling it. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ic6c76375df465a4ad2e20dd7add7037477d973c1
2023-09-08Merge changes from topic "sm/errata_X3" into integrationBipin Ravi
* changes: fix(cpus): workaround for Cortex-X3 erratum 2742421 feat(errata_abi): add support for Cortex-X3
2023-09-07fix(cpus): workaround for Cortex-X3 erratum 2742421Sona Mathew
Cortex-X3 erratum 2742421 is a Cat B erratum that applies to all revisions <= r1p1 and is fixed in r1p2. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com> Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b
2023-09-07feat(errata_abi): add support for Cortex-X3Sona Mathew
Add errata ABI support for Cortex-X3 CPU. Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com> Change-Id: Ifb68178948860cafe25b351f20c480c847608a1b
2023-08-29fix(cpus): workaround for Neoverse N2 erratum 2009478Bipin Ravi
Neoverse N2 erratum 2009478 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to clear the ED bit for all core error records before setting the PWRDN_EN bit in CPUPWRCTLR_EL1 to request a power down. SDEN documentation: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ic5ef58c9e795b90026af1d2b09edc0eea3ceee51
2023-08-03fix(cpus): workaround for Neoverse N2 erratum 2779511Arvind Ram Prakash
Neoverse N2 erratum 2779511 is a Cat B erratum that applies to all revisions <=r0p2 and is fixed in r0p3. The workaround is to set bit[47] of CPUACTLR3_EL1 SDEN documentation: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: Iaa0e30de8473ecb1df1fcca3a45904aac2e419b3
2023-08-03fix(cpus): workaround for Neoverse N2 erratum 2743014Arvind Ram Prakash
Neoverse N2 erratum 2743014 is a Cat B erratum that applies to all revisions <=r0p2 and is fixed in r0p3. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: Ie7e1be5dea9d1f74738f9fed0fb58bfd41763192
2023-07-21fix(cpus): workaround for Neoverse V2 erratum 2801372Moritz Fischer
Neoverse V2 erratum 2801372 is a Cat B erratum that applies to all revisions <=r0p1 and is fixed in r0p2. The workaround is to insert a dsb before the isb in the power down sequence. This errata is explained in SDEN 2332927 available at: https://developer.arm.com/documentation/SDEN2332927 Change-Id: I8716b9785a67270a72ae329dc49a2f2239dfabff Signed-off-by: Moritz Fischer <moritzf@google.com>
2023-05-30chore: rename Makalu to Cortex-A715Harrison Mutai
Change-Id: I017c955cb643e2befb6b01e1b5a07c22172b08b9 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-05-05fix(cpus): workaround platforms non-arm interconnectSona Mathew
The workarounds for these below mentioned errata are not implemented in EL3, but the flags can be enabled/disabled at a platform level based on arm/non-arm interconnect IP. The ABI helps assist the Kernel in the process of mitigation for the following errata: Cortex-A715: erratum 2701951 Neoverse V2: erratum 2719103 Cortex-A710: erratum 2701952 Cortex-X2: erratum 2701952 Neoverse N2: erratum 2728475 Neoverse V1: erratum 2701953 Cortex-A78: erratum 2712571 Cortex-A78AE: erratum 2712574 Cortex-A78C: erratum 2712575 EL3 provides an appropriate return value via errata ABI when the kernel makes an SMC call using the EM_CPU_ERRATUM_FEATURES FID with the appropriate erratum ID. Change-Id: I35bd69d812dba37410dd8bc2bbde20d4955b0850 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
2023-05-05refactor(errata_abi): factor in non-arm interconnectSona Mathew
Workaround to help enable the kernel to query errata status using the errata abi feature for platforms with a non-arm interconnect. Change-Id: I47b03eaee5a0a763056ae71883fa30dfacb9b3f7 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
2023-05-05feat(errata_abi): errata management firmware interfaceSona Mathew
This patch adds the errata management firmware interface for lower ELs to discover details about CPU erratum. Based on the CPU erratum identifier the interface enables the OS to find the mitigation of an erratum in EL3. The ABI can only be present in a system that is compliant with SMCCCv1.1 or higher. This implements v1.0 of the errata ABI spec. For details on all possible return values, refer the design documentation below: ABI design documentation: https://developer.arm.com/documentation/den0100/1-0?lang=en Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com> Change-Id: I70f0e2569cf92e6e02ad82e3e77874546232b89a
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