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2023-10-26Merge changes from topic "sm/err_errata" into integrationLauren Wehrmeister
* changes: fix(cpus): fix the rev-var of Neoverse-V1 fix(errata-abi): update the Neoverse-N2 errata ABI struct fix(errata-abi): update the neoverse-N1 errata ABI struct fix(cpus): fix the rev-var of Cortex-X2 fix(errata-abi): update the Cortex-A78C errata ABI struct fix(cpus): update the rev-var for Cortex-A78AE fix(errata-abi): update the Cortex-A76 errata ABI struct fix(cpus): fix the rev-var for Cortex-A710
2023-10-24fix(cpus): workaround for Cortex-A510 erratum 2080326Sona Mathew
Cortex-A510 erratum 2080326 is a Cat B erratum that applies to all revisions <= r0p2 and is fixed in r0p3. The workaround sequence helps perform a DSB after each TLBI instruction and can be applied only for version r0p2 and has minimal performance impact. The workaround is not applicable for versions < r0p2. SDEN documentation: https://developer.arm.com/documentation/SDEN1873361/latest Change-Id: Ib9bce8b711c25a79f7b2f891ae6f8b366fc80ddd Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): fix the rev-var of Neoverse-V1Sona Mathew
Update the revision and variant information in the errata ABI file, neoverse_v1.S file for erratum ID - 2294912 to match the revision and variant in the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1401781/latest Change-Id: I38a0f53c3515860ba442b5c0872c8ab051fdda6f Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): fix the rev-var of Cortex-X2Sona Mathew
Update the revision and variant information in the errata ABI file, cortex_X2.S file for erratum ID - 2058056 to match the revision and variant in the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775100/latest Change-Id: I28ee39949d977c53d6f5243100f0c29bc3c0428c Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): update the rev-var for Cortex-A78AESona Mathew
Update the revision and variant information in the cortex_a78_ae.s and errata ABI file for erratum ID - 2376748 based on the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1707912/latest Change-Id: I082aac41adf717b0d5d59046a8933a3f5a3de94f Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): fix the rev-var for Cortex-A710Sona Mathew
Update the revision and variant information in the errata ABI file, cortex_A710.S file for erratum ID - 2058056 and erratum ID - 2055002 to match the revision and variant in the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest Change-Id: Ie010dae90dabf8670f588a06f9a606cf41e22afa Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-04fix(cpus): workaround for Cortex-X3 erratum 2070301Sona Mathew
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all revisions <= r1p2 and is still open. The workaround is to write the value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher in the most conservative mode instead of disabling it. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-09-22Merge changes from topic "errata" into integrationLauren Wehrmeister
* changes: fix(cpus): workaround for Neoverse V2 erratum 2743011 fix(cpus): workaround for Neoverse V2 erratum 2779510 fix(cpus): workaround for Neoverse V2 erratum 2719105 fix(cpus): workaround for Neoverse V2 erratum 2331132
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2743011Bipin Ravi
Neoverse V2 erratum 2743011 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I0e06ca723a1cce51fb027b7160f3dd06a4c93e64
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2779510Bipin Ravi
Neoverse V2 erratum 2779510 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The workaround is to set bit[47] of CPUACTLR3_EL1 which might have a small impact on power and negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I6d937747bdcbf2913a64c4037f99918cbc466e80
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2719105Bipin Ravi
Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2331132Bipin Ravi
Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all revisions <= r0p2 and is still open. The workaround is to write the value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register which will place the data prefetcher in the most conservative mode instead of disabling it. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ic6c76375df465a4ad2e20dd7add7037477d973c1
2023-09-08Merge changes from topic "sm/errata_X3" into integrationBipin Ravi
* changes: fix(cpus): workaround for Cortex-X3 erratum 2742421 feat(errata_abi): add support for Cortex-X3
2023-09-07fix(cpus): workaround for Cortex-X3 erratum 2742421Sona Mathew
Cortex-X3 erratum 2742421 is a Cat B erratum that applies to all revisions <= r1p1 and is fixed in r1p2. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com> Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b
2023-08-29fix(cpus): workaround for Neoverse N2 erratum 2009478Bipin Ravi
Neoverse N2 erratum 2009478 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to clear the ED bit for all core error records before setting the PWRDN_EN bit in CPUPWRCTLR_EL1 to request a power down. SDEN documentation: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ic5ef58c9e795b90026af1d2b09edc0eea3ceee51
2023-08-03fix(cpus): workaround for Neoverse N2 erratum 2779511Arvind Ram Prakash
Neoverse N2 erratum 2779511 is a Cat B erratum that applies to all revisions <=r0p2 and is fixed in r0p3. The workaround is to set bit[47] of CPUACTLR3_EL1 SDEN documentation: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: Iaa0e30de8473ecb1df1fcca3a45904aac2e419b3
2023-08-03fix(cpus): workaround for Neoverse N2 erratum 2743014Arvind Ram Prakash
Neoverse N2 erratum 2743014 is a Cat B erratum that applies to all revisions <=r0p2 and is fixed in r0p3. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: Ie7e1be5dea9d1f74738f9fed0fb58bfd41763192
2023-08-03fix(docs): updated certain Neoverse N2 erratum status in docsArvind Ram Prakash
Certain Neoverse N2 erratum in docs were out of date with the latest SDEN document and hence updated it to match the latest SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I5d82a56388a46a09a42b940a633ecebdde0c74e3
2023-07-21fix(cpus): workaround for Neoverse V2 erratum 2801372Moritz Fischer
Neoverse V2 erratum 2801372 is a Cat B erratum that applies to all revisions <=r0p1 and is fixed in r0p2. The workaround is to insert a dsb before the isb in the power down sequence. This errata is explained in SDEN 2332927 available at: https://developer.arm.com/documentation/SDEN2332927 Change-Id: I8716b9785a67270a72ae329dc49a2f2239dfabff Signed-off-by: Moritz Fischer <moritzf@google.com>
2023-05-05fix(cpus): workaround platforms non-arm interconnectSona Mathew
The workarounds for these below mentioned errata are not implemented in EL3, but the flags can be enabled/disabled at a platform level based on arm/non-arm interconnect IP. The ABI helps assist the Kernel in the process of mitigation for the following errata: Cortex-A715: erratum 2701951 Neoverse V2: erratum 2719103 Cortex-A710: erratum 2701952 Cortex-X2: erratum 2701952 Neoverse N2: erratum 2728475 Neoverse V1: erratum 2701953 Cortex-A78: erratum 2712571 Cortex-A78AE: erratum 2712574 Cortex-A78C: erratum 2712575 EL3 provides an appropriate return value via errata ABI when the kernel makes an SMC call using the EM_CPU_ERRATUM_FEATURES FID with the appropriate erratum ID. Change-Id: I35bd69d812dba37410dd8bc2bbde20d4955b0850 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
2023-03-21fix(cpus): workaround for Cortex-A78C erratum 1827440Bipin Ravi
Cortex-A78C erratum 1827440 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[2], which forces atomic store operations to write-back memory to be performed in the L1 data cache. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I41d8ef48f70216ec66bf2b0f4f03ea8d8c261ee7
2023-03-21fix(cpus): workaround for Cortex-A78C erratum 1827430Bipin Ravi
Cortex-A78C erratum 1827430 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set the CPUECTLR_EL1[53] to 1, which disables allocation of splintered pages in the L2 TLB. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ie68771bdd3bddeff54d06b6a456dad4a7fc27426
2023-03-16refactor(cpus): shorten errata flag definesBoyan Karatotev
The cpu-ops makefile has errata flag definition and flag processing done per flag in separate parts in the file. Rework this to make a list and do this in a much more concise way. To ensure no flags were missed, a bash script [1] was used to verify all errata flags made it across. Only the first few flags with different naming were checked manually. [1]: sed -n "s/CPU_FLAG_LIST += ERRATA_\(.*\)/\1/p" lib/cpus/cpu-ops.mk > \ /tmp/new git checkout origin/master sed -n "s/ERRATA_\([[:alnum:]_-]*\)\s*?=0/\1/p" lib/cpus/cpu-ops.mk > \ /tmp/old diff /tmp/old /tmp/new Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I3b88af46838cc26f42d2c66b31f96c0855fa406c
2023-03-14Merge "fix(cpus): workaround for Neoverse V1 errata 2743233" into integrationBipin Ravi
2023-03-09fix(cpus): workaround for Neoverse V1 errata 2743233Sona Mathew
Neoverse V1 erratum 2743233 is a Cat B erratum that applies to all revisions <= r1p2 and is still open. The workaround sets CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN1401781/latest Change-Id: If51a6f4293fa8b5b35c44edd564ebb715ba309a1 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
2023-03-08fix(cpus): workaround for Cortex-A78C erratum 2779484Bipin Ravi
Cortex-A78C erratum 2779484 is a Cat B erratum that applies to revisions r0p1 and r0p2 and is still open. The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this bit might have a small impact on power and negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/SDEN2004089/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I9a8c16a845c3ba6eb2f17a5119aa6ca09a0d27ed
2023-03-08fix(cpus): workaround for Cortex-A78 erratum 2742426Bipin Ravi
Cortex-A78 erratum 2742426 is a Cat B erratum that applies to all revisions <= r1p2 and is still open. The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN1401784/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1
2023-01-27Merge "fix(cpus): workaround for Cortex-A78C erratum 2772121" into integrationLauren Wehrmeister
2023-01-26Merge "fix(cpus): workaround for Cortex-A510 erratum 2684597" into integrationLauren Wehrmeister
2023-01-25fix(cpus): workaround for Cortex-A510 erratum 2684597Harrison Mutai
Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The workaround is to execute a TSB CSYNC and DSB before executing WFI for power down. SDEN can be found here: https://developer.arm.com/documentation/SDEN1873361/latest https://developer.arm.com/documentation/SDEN1873351/latest Change-Id: Ic0b24b600bc013eb59c797401fbdc9bda8058d6d Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-01-19fix(cpus): workaround for Neoverse V1 errata 2779461Sona Mathew
Neoverse V1 erratum 2779461 is a Cat B erratum that applies to all revisions <=r1p2 and is still open. The workaround sets CPUACTLR3_EL1[47] bit to 1. Setting this bit might have a small impact on power and negligible impact on performance. SDEN documentation:https://developer.arm.com/documentation/SDEN1401781/latest Change-Id: I367cda1779684638063d7292fda20ca6734e6f10 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
2023-01-19fix(cpus): workaround for Cortex-A78 erratum 2779479Sona Mathew
Cortex-A78 erratum 2779479 is a Cat B erratum that applies to all revisions <= r1p2 and is still open. The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this bit might have a small impact on power and negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/SDEN1401784/latest Change-Id: I3779fd1eff3017c5961ffa101b357918070b3b36 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
2023-01-18fix(cpus): workaround for Cortex-A78C erratum 2772121Bipin Ravi
Cortex-A78C erratum 2772121 is a Cat B erratum that applies to all revisions <=r0p2 and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I0e190dabffc20c4d3b9b98d1abeb50f308b80bb9
2023-01-11Merge "fix(cpus): workaround for Cortex-X2 erratum 2282622" into integrationMadhukar Pappireddy
2023-01-11Merge "fix(cpus): workaround for Cortex-A710 erratum 2282622" into integrationLauren Wehrmeister
2023-01-11fix(cpus): workaround for Cortex-X2 erratum 2282622Bipin Ravi
Cortex-X2 erratum 2282622 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround is to set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. SDEN documentation: https://developer.arm.com/documentation/SDEN1775100/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I43956aa4898a8608eedc5d0dd1471172c641a0c6
2023-01-09fix(cpus): workaround for Cortex-A710 erratum 2282622Bipin Ravi
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround was earlier applied to all revisions <= r2p0, this patch extends it to r2p1. This was thought to have been fixed in r2p1 which is not the case. SDEN documentation: https://developer.arm.com/documentation/SDEN1775101/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Iad38a7fe57bec3f2d8977995acd601dcd9ae69c0
2022-12-21fix(cpus): workaround for Neoverse N2 erratum 2743089Bipin Ravi
Neoverse N2 erratum 2743089 is a Cat B erratum that applies to all revisions <=r0p2 and is fixed in r0p3. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Idec862226bd32c91374a8bbd5d73d7ee480a34d9
2022-12-20fix(cpus): workaround for Cortex-A78 erratum 2772019Bipin Ravi
Cortex-A78 erratum 2772019 is a Cat B erratum that applies to all revisions <=r1p2 and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN1401784/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I0362da463eca777aa7a385bcdeb39b8549799f02
2022-12-20fix(cpus): workaround for Neoverse V1 erratum 2743093Bipin Ravi
Neoverse V1 erratum 2743093 is a Cat B erratum that applies to all revisions <=r1p2 and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN1401781/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I8ee7c16c14c4fd6ee35d20c855273ecfce0d1b32
2022-12-07fix(cpus): workaround for Cortex-X2 erratum 2768515Bipin Ravi
Cortex-X2 erratum 2768515 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN1775100/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ib02688f7b6dc7f6ec305e68e8895174f6fd577a0
2022-12-07fix(cpus): workaround for Cortex-A710 erratum 2768515Bipin Ravi
Cortex-A710 erratum 2768515 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN1775101/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: If17fe04d3fda0dba6b8aabdd837a1c53e1830ed5
2022-11-17fix(cpus): workaround for Cortex-X3 erratum 2615812Harrison Mutai
Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1, and is still open. The workaround is to disable the use of the Full Retention power mode in the core (setting WFI_RET_CTRL and WFE_RET_CTRL in CORTEX_X3_IMP_CPUPWRCTLR_EL1 to 0b000). SDEN can be found here: https://developer.arm.com/documentation/SDEN2055130/latest Change-Id: I5ad66df3e18fc85a6b23f6662239494ee001d82f Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2022-11-10fix(cpus): workaround for Cortex-A77 erratum 2743100Boyan Karatotev
Cortex-A77 erratum 2743100 is a Cat B erratum that applies to revisions r0p0, r1p0, r1p1, and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN can be found here: https://developer.arm.com/documentation/SDEN1152370/latest Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I8e49a2dac8611f31ace249a17ae7a90cd60e742a
2022-11-03fix(cpus): workaround for Cortex-A76 erratum 2743102Bipin Ravi
Cortex-A76 erratum 2743102 is a Cat B erratum that applies to all revisions <=r4p1 and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN885749/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ie2cd73bd91417d30b5633d80b2fbee32944bc2de
2022-11-03fix(cpus): workaround for Neoverse N1 erratum 2743102Bipin Ravi
Neoverse N1 erratum 2743102 is a Cat B erratum that applies to all revisions <=r4p1 and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN885747/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I81a8793c1a118764df3ac97b67f5e088f56f6a20
2022-10-27fix(cpus): workaround for Cortex-A710 erratum 2291219Boyan Karatotev
Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set CPUACTLR2_EL1[36] to 1 before the power down sequence that sets CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents the deadlock. TF-A never clears this bit even if it wakes up from the wfi in the sequence since it is not expected to do anything but retry to power down after and the bit is cleared on reset. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775101/latest Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I7d3a97dfac0c433c0be386c1f3d2f2e895a3f691
2022-10-27fix(cpus): workaround for Cortex-X3 erratum 2313909Boyan Karatotev
Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions r0p0 and r1p0, and is fixed in r1p1. The workaround is to set CPUACTLR2_EL1[36] to 1 before the power down sequence that sets CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents the deadlock. TF-A never clears this bit even if it wakes up from the wfi in the sequence since it is not expected to do anything but retry to power down after and the bit is cleared on reset. SDEN can be found here: https://developer.arm.com/documentation/SDEN2055130/latest Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I5935b4bcd1e6712477c0d6eab2acc96d7964a35d
2022-10-27fix(cpus): workaround for Neoverse-N2 erratum 2326639Boyan Karatotev
Neoverse-N2 erratum 2326639 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[36] to 1 before the power down sequence that sets CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents the deadlock. TF-A never clears this bit even if it wakes up from the wfi in the sequence since it is not expected to do anything but retry to power down after and the bit is cleared on reset. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest/ Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I9a325c5b9b498798e5efd5c79a4a6d5bed97c619
2022-10-13fix(cpus): workaround for Cortex-A510 erratum 2666669Akram Ahmad
Cortex-A510 erratum 2666669 applies to revisions r1p1 and lower, and is fixed in r1p2. The errata is mitigated by setting IMP_CPUACTLR_EL1[38] to 1. SDEN documentation: https://developer.arm.com/documentation/SDEN1873351/latest https://developer.arm.com/documentation/SDEN1873361/latest Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com> Change-Id: Ief27e4a155e43e75f05f2710d0c7bd5da2dec43f
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