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2023-11-02fix(cpus): workaround for Cortex-X2 erratum 2742423Bipin Ravi
Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all revisions <= r2p1 and is still open. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775100/latest Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-11-02fix(cpus): workaround for Cortex-A710 erratum 2742423Bipin Ravi
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all revisions <= r2p1 and is still open. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-11-02fix(cpus): workaround for Neoverse N2 erratum 2340933Bipin Ravi
Neoverse N2 erratum 2340933 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR5_EL1[61] to 1. SDEN documentation: https://developer.arm.com/documentation/SDEN-1982442/latest Change-Id: I121add0dd35072c53392d33f049d893a5ff6354f Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-11-02fix(cpus): workaround for Neoverse N2 erratum 2346952Bipin Ravi
Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all revisions <= r0p2 and is fixed in r0p3. The workaround is to set L2 TQ size statically to it's full size. SDEN documentation: https://developer.arm.com/documentation/SDEN-1982442/latest Change-Id: I03c3cf1f951fbc906fdebcb99a523c5ac8ba055d Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-10-27Merge "feat(cpus): add support for Travis CPU" into integrationMadhukar Pappireddy
2023-10-26Merge changes from topic "sm/err_errata" into integrationLauren Wehrmeister
* changes: fix(cpus): fix the rev-var of Neoverse-V1 fix(errata-abi): update the Neoverse-N2 errata ABI struct fix(errata-abi): update the neoverse-N1 errata ABI struct fix(cpus): fix the rev-var of Cortex-X2 fix(errata-abi): update the Cortex-A78C errata ABI struct fix(cpus): update the rev-var for Cortex-A78AE fix(errata-abi): update the Cortex-A76 errata ABI struct fix(cpus): fix the rev-var for Cortex-A710
2023-10-26feat(cpus): add support for Travis CPUJuan Pablo Conde
Adding basic CPU library code to support Travis CPU Change-Id: I3c85e9fab409325d213978888a8f6d6949291258 Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
2023-10-24fix(cpus): workaround for Cortex-A510 erratum 2080326Sona Mathew
Cortex-A510 erratum 2080326 is a Cat B erratum that applies to all revisions <= r0p2 and is fixed in r0p3. The workaround sequence helps perform a DSB after each TLBI instruction and can be applied only for version r0p2 and has minimal performance impact. The workaround is not applicable for versions < r0p2. SDEN documentation: https://developer.arm.com/documentation/SDEN1873361/latest Change-Id: Ib9bce8b711c25a79f7b2f891ae6f8b366fc80ddd Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): fix the rev-var of Neoverse-V1Sona Mathew
Update the revision and variant information in the errata ABI file, neoverse_v1.S file for erratum ID - 2294912 to match the revision and variant in the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1401781/latest Change-Id: I38a0f53c3515860ba442b5c0872c8ab051fdda6f Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): fix the rev-var of Cortex-X2Sona Mathew
Update the revision and variant information in the errata ABI file, cortex_X2.S file for erratum ID - 2058056 to match the revision and variant in the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775100/latest Change-Id: I28ee39949d977c53d6f5243100f0c29bc3c0428c Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): update the rev-var for Cortex-A78AESona Mathew
Update the revision and variant information in the cortex_a78_ae.s and errata ABI file for erratum ID - 2376748 based on the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1707912/latest Change-Id: I082aac41adf717b0d5d59046a8933a3f5a3de94f Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-24fix(cpus): fix the rev-var for Cortex-A710Sona Mathew
Update the revision and variant information in the errata ABI file, cortex_A710.S file for erratum ID - 2058056 and erratum ID - 2055002 to match the revision and variant in the latest SDEN. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest Change-Id: Ie010dae90dabf8670f588a06f9a606cf41e22afa Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-10-04fix(cpus): workaround for Cortex-X3 erratum 2070301Sona Mathew
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all revisions <= r1p2 and is still open. The workaround is to write the value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher in the most conservative mode instead of disabling it. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-09-22Merge changes from topic "errata" into integrationLauren Wehrmeister
* changes: fix(cpus): workaround for Neoverse V2 erratum 2743011 fix(cpus): workaround for Neoverse V2 erratum 2779510 fix(cpus): workaround for Neoverse V2 erratum 2719105 fix(cpus): workaround for Neoverse V2 erratum 2331132
2023-09-21fix(cpus): update the fix for Cortex-A78AE erratum 1941500Varun Wadekar
This patch fixes the mitigation for erratum 1941500 for the Cortex-A78AE CPUs. The right fix is to set the bit 8, whereas the current code clears it. Reported-by: matthias.rosenfelder@nio.io Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ib7c3fddd567eeae6204756377e0f77a573c0a911
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2743011Bipin Ravi
Neoverse V2 erratum 2743011 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I0e06ca723a1cce51fb027b7160f3dd06a4c93e64
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2779510Bipin Ravi
Neoverse V2 erratum 2779510 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The workaround is to set bit[47] of CPUACTLR3_EL1 which might have a small impact on power and negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I6d937747bdcbf2913a64c4037f99918cbc466e80
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2719105Bipin Ravi
Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba
2023-09-18fix(cpus): workaround for Neoverse V2 erratum 2331132Bipin Ravi
Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all revisions <= r0p2 and is still open. The workaround is to write the value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register which will place the data prefetcher in the most conservative mode instead of disabling it. SDEN documentation: https://developer.arm.com/documentation/SDEN2332927/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ic6c76375df465a4ad2e20dd7add7037477d973c1
2023-09-08Merge changes from topic "sm/errata_X3" into integrationBipin Ravi
* changes: fix(cpus): workaround for Cortex-X3 erratum 2742421 feat(errata_abi): add support for Cortex-X3
2023-09-07fix(cpus): workaround for Cortex-X3 erratum 2742421Sona Mathew
Cortex-X3 erratum 2742421 is a Cat B erratum that applies to all revisions <= r1p1 and is fixed in r1p2. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com> Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b
2023-09-07Merge "fix(cpus): workaround for Neoverse N2 erratum 2009478" into integrationMark Dykes
2023-08-29fix(cpus): workaround for Neoverse N2 erratum 2009478Bipin Ravi
Neoverse N2 erratum 2009478 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to clear the ED bit for all core error records before setting the PWRDN_EN bit in CPUPWRCTLR_EL1 to request a power down. SDEN documentation: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ic5ef58c9e795b90026af1d2b09edc0eea3ceee51
2023-08-29Merge "feat(cpus): add support for Nevis CPU" into integrationBipin Ravi
2023-08-28feat(cpus): add support for Nevis CPUJuan Pablo Conde
Adding basic CPU library code to support Nevis CPU Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
2023-08-28Merge changes from topic "sm_bk/errata_refactor" into integrationBipin Ravi
* changes: refactor(cpus): convert the Cortex-A57 to use cpu helpers refactor(cpus): convert the Cortex-A57 to use the errata framework refactor(cpus): reorder Cortex-A57 errata by ascending order refactor(cpus): add Cortex-A57 errata framework information refactor(cpus): convert the Cortex-A53 to use cpu helpers refactor(cpus): convert the Cortex-A53 to use the errata framework refactor(cpus): reorder Cortex-A53 errata by ascending order
2023-08-24refactor(cpus): convert the Cortex-A57 to use cpu helpersBoyan Karatotev
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I1cc10fa91cb9c837386144249dafeb6178d5866e
2023-08-24refactor(cpus): convert the Cortex-A57 to use the errata frameworkBoyan Karatotev
This involves replacing: * the reset_func with the standard cpu_reset_func_{start,end} to apply errata automatically * the <cpu>_errata_report with the errata_report_shim to report errata automatically ...and for each erratum: * the prologue with the workaround_<type>_start to do the checks and framework registration automatically * the epilogue with the workaround_<type>_end * the checker function with the check_erratum_<type> to make it more descriptive It is important to note that the errata workaround sequences remain unchanged and preserve their git blame. At this point the binary output of all errata was checked with the script from commit 19136. All reported discrepancies involve errata with no workaround in the cpu file or errata that did not previously have a workaround function and now do. The non temporal hint erratum has been converted to a numeric erratum. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Ib321ab01362c5954fe78e7349229c1437b3da847
2023-08-24refactor(cpus): reorder Cortex-A57 errata by ascending orderBoyan Karatotev
Errata report order is enforced to be in ascending order. To achieve this with the errata framework this has to be done at the definition level. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Ia98976797fc0811f30c7dbf714e94b36e3c2263e
2023-08-24refactor(cpus): convert the Cortex-A53 to use cpu helpersBoyan Karatotev
Also, convert checker functions of errata which are enabled for all cpu revisions to report correctly in preparation of the errata ABI. Although the script from commit 250919 was used to check that errata code did not change, this CPU only loosely adhered to convention and its output was not particularly useful. Nevertheless, the discrepancies were manually verified. All errata have been checked that they get invoked. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I988db6e7b6d1732f1d2258dbdf945cb475781894
2023-08-24refactor(cpus): convert the Cortex-A53 to use the errata frameworkBoyan Karatotev
This involves replacing: * the reset_func with the standard cpu_reset_func_{start,end} to apply errata automatically * the <cpu>_errata_report with the errata_report_shim to report errata automatically ...and for each erratum: * the prologue with the workaround_<type>_start to do the checks and framework registration automatically * the epilogue with the workaround_<type>_end * the checker function with the check_erratum_<type> to make it more descriptive It is important to note that the errata workaround and checking sequences remain unchanged and preserve their git blame. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I30556f438859d17f054cb6bc96f3069b40474b58
2023-08-24refactor(cpus): reorder Cortex-A53 errata by ascending orderBoyan Karatotev
Errata report order is enforced to be in ascending order. To achieve this with the errata framework this has to be done at the definition level. Also rename the disable_non_temporal_hint to its erratum number to conform to convention. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Id474872afebf361ab3d21c454ab3624db8354045
2023-08-24fix(cpus): check for SME presence in GelasJuan Pablo Conde
The original powerdown function for Gelas included SME disabling instructions but did not check for the presence of SME before disabling. This could lead to unexpected beaviors. This patch adds that check so the feature is disabled only if it is present. Change-Id: I582db53a6669317620e4f72a3eac87525897d3d0 Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
2023-08-14Merge "feat(cpus): add support for Gelas CPU" into integrationLauren Wehrmeister
2023-08-11feat(cpus): add support for Gelas CPUJuan Pablo Conde
This patch adds the necessary CPU library code to support the Gelas CPU Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3 Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
2023-08-11Merge changes from topic "ar/errata_refactor" into integrationBipin Ravi
* changes: refactor(cpus): convert Neoverse Poseidon to use CPU helpers refactor(cpus): convert Neoverse Poseidon to framework
2023-08-11refactor(cpus): convert Neoverse Poseidon to use CPU helpersArvind Ram Prakash
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: Icf406c05cdb8d62cd0f41a5f19ae5376707e69bd
2023-08-11refactor(cpus): convert Neoverse Poseidon to frameworkArvind Ram Prakash
This involves replacing: * the reset_func with the standard cpu_reset_func_{start,end} to apply errata automatically * the <cpu>_errata_report with the errata_report_shim to report errata automatically ...and for each erratum: * the prologue with the workaround_<type>_start to do the checks and framework registration automatically * the epilogue with the workaround_<type>_end * the checker function with the check_erratum_<type> to make it more descriptive It is important to note that the errata workaround sequences remain unchanged and preserve their git blame. Testing was conducted by: * Manual comparison of disassembly of converted functions with non- converted functions aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf vs aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf * Build for release with all errata flags enabled and run default tftf tests CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp DEBUG=0 \ CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 \ BL33=./../tf-a-tests/build/fvp/release/tftf.bin \ WORKAROUND_CVE_2022_23960=1 ERRATA_ABI_SUPPORT=1 all fip * Build for debug with all errata enabled and step through ArmDS at reset to ensure all functions are entered. Change-Id: I34e27e468d4f971423a03a95a4a52f4af8bd783a Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
2023-08-11Merge changes from topic "ar/errata_refactor" into integrationLauren Wehrmeister
* changes: refactor(cpus): convert Neoverse V2 to use CPU helpers refactor(cpus): convert Neoverse V2 to framework
2023-08-10refactor(cpus): convert Neoverse V2 to use CPU helpersMoritz Fischer
Convert Neoverse V2 to use CPU helpers, in this case that's only two spots. Change-Id: Icd250f92974e8a50c459038de7644a2e68007589 Signed-off-by: Moritz Fischer <moritzf@google.com> Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
2023-08-10refactor(cpus): convert Neoverse V2 to frameworkMoritz Fischer
For V2, this involves replacing: - The reset_func with the standard cpu_reset_func_{start,end} to apply errata automatically - The <cpu>_errata_report with the errata_report_shim to report errata automatically And for each erratum: - The prologue with the workaround_<type>_start to do the checks and framework registration automatically at reset or runtime - The epilogue with the workaround_<type>_end - The checker function with the check_erratum_<type> to check whether the erratum applies on the revision of the CPU. It is important to note that the errata workaround sequences remain unchanged and preserve their git blame. Testing was conducted by: * Manual comparison of disassembly of converted functions with non- converted functions aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf vs aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf * Build for release with all errata flags enabled and run default tftf tests CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp CTX_INCLUDE_AARCH32_REGS=0 \ HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 \ BL33=./../tf-a-tests/build/fvp/debug/tftf.bin \ ERRATA_V2_2801372 WORKAROUND_CVE_2022_23960=1 ERRATA_ABI_SUPPORT=1 all fip * Build for debug with all errata enabled and step through ArmDS at reset to ensure all functions are entered. Change-Id: Ic968844d6aabea3867189d747769ced8faa87e56 Signed-off-by: Moritz Fischer <moritzf@google.com> Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
2023-08-10fix(cpus): assert invalid cpu_ops obtainedThaddeus Serna
Not including the proper CPU file can halt execution at the reset_handler since the cpu_ops obtained will be invalid and therefore the cpu reset function will be invalid too, unless SUPPORT_UNKNOWN_MPID is enabled. This patch adds an assert to check for the validity of the obtained cpu_ops object and will display an error if the object is invalid. Change-Id: I0e1661745e4a692aab5e910e110c2de0caf64f46 Signed-off-by: Thaddeus Serna <Thaddeus.Gonzalez-Serna@arm.com>
2023-08-08Merge "fix(cpus): revert erroneous use of override_vector_table macro in ↵Bipin Ravi
Cortex-A73" into integration
2023-08-08Merge "chore: update to use Arm word across TF-A" into integrationManish V Badarkhe
2023-08-08chore: update to use Arm word across TF-AGovindraj Raja
Align entire TF-A to use Arm in copyright header. Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-08-07fix(cpus): revert erroneous use of override_vector_table macro in Cortex-A73Sona Mathew
override_vector_table does adr, followed by an msr ops. Accidentally was used here for for adr and mrs op. Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com> Change-Id: I2d3fda12acd097acabbde9b7dcc376d08419e223
2023-08-07refactor(cpus): convert the Cortex-A710 to use cpu helpersHarrison Mutai
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com> Change-Id: I5e928f139c2e9fa91c78947cf6a8bff546f7be05
2023-08-07refactor(cpus): convert Cortex-A710 to use the errata frameworkHarrison Mutai
This involves replacing: * the reset_func with the standard cpu_reset_func_{start,end} to apply errata automatically * the <cpu>_errata_report with the errata_report_shim to report errata automatically ...and for each erratum: * the prologue with the workaround_<type>_start to do the checks and framework registration automatically * the epilogue with the workaround_<type>_end * the checker function with the check_erratum_<type> to make it more descriptive It is important to note that the errata workaround and checking sequences remain unchanged and preserve their git blame. Testing was conducted by: * Building for release with all errata flags enabled and running script in change 19136 to compare output of objdump for each errata. * Manual comparison of disassembly of converted functions with non- converted functions * Build for debug with all errata enabled and step through ArmDS at reset to ensure all functions are entered. Signed-off-by: Harrison Mutai <harrison.mutai@arm.com> Change-Id: I417539ab292f13a4f0949625d2fef6b7792fbd35
2023-08-07refactor(cpus): reorder Cortex-A710 errata by ascending orderHarrison Mutai
Errata report order is enforced to be in ascending order. To achieve this with the errata framework this has to be done at the definition level. Change-Id: I4a6ed55d48e91ec914b7a591c6d30da5ce5d915d Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-08-05Merge changes from topic "sm/errata_refactor" into integrationBipin Ravi
* changes: refactor(cpus): convert Cortex-A15 to use the errata framework refactor(cpus): convert the Cortex-X3 to use the cpu helpers refactor(cpus): convert Cortex-X3 to use the errata framework refactor(cpus): reorder Cortex-X3 errata by ascending order refactor(cpus): convert the Cortex-A73 to use the cpu helpers refactor(cpus): convert Cortex-A73 to use the errata framework refactor(cpus): reorder Cortex-A73 errata by ascending order refactor(cpus): convert the Cortex-A35 to use the cpu helpers refactor(cpus): convert Cortex-A35 to use the errata framework
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-23 09:45:56 +0000