summaryrefslogtreecommitdiff
path: root/lib/cpus/aarch64/neoverse_n1.S
AgeCommit message (Collapse)Author
2023-07-26refactor(cpus): convert Neoverse-N1 to use helperslaurenw-arm
Conversion to use CPU helpers for Neoverse-N1 testing done with framework adaptation patch. Change-Id: I2103f6e64daf0ee4c7b756083e5bf485f15c0e21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2023-07-26refactor(cpus): convert Neoverse-N1 to frameworklaurenw-arm
For N1, this involves replacing: - The reset_func with the standard cpu_reset_func_{start,end} to apply errata automatically - The <cpu>_errata_report with the errata_report_shim to report errata automatically And for each erratum: - The prologue with the workaround_<type>_start to do the checks and framework registration automatically at reset or runtime - The epilogue with the workaround_<type>_end - The checker function with the check_erratum_<type> to check whether the erratum applies on the revision of the CPU. Testing was conducted by: - Manual comparison of disassembly of converted functions with non- converted functions: aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf vs aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf - Build for debug with all errata enabled and step through ArmDS to ensure all functions are entered and the path remains the same as before conversion to the new framework. Change-Id: I2ea612d4c197dd73835fadda81f59732c19534f8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2023-07-18refactor(cpus): reorder Neoverse-N1 .S filelaurenw-arm
Moving neoverse_n1_disable_speculative_loads function before reset function to maintain git blame with refactor to new framework. Change-Id: I79a4de9955a6f37e289456a743b946c0c4c8c27f Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2023-04-24fix(cpus): do not put RAS check before using esbManish Pandey
If RAS Extension is not implemented esb instruction executes as a NOP. No need to have a check for RAS presence in the code. Also, The handler is related to a synchronous exceptions which implicitly is part of BL31 image only, so remove that check too. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: If4264504cba9f0642b7b9c581ae66cd4deace32b
2023-03-27refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1Andre Przywara
So far we have the ENABLE_AMU build option to include AMU register handling code for enabling and context switch. There is also an ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system register handling. The latter needs some alignment with the new feature scheme, but it conceptually overlaps with the ENABLE_AMU option. Since there is no real need for two separate options, unify both into a new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at this point, a subsequent patch will make use of the new feature handling scheme. Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-03fix(cpus): workaround for Neoverse N1 erratum 2743102Bipin Ravi
Neoverse N1 erratum 2743102 is a Cat B erratum that applies to all revisions <=r4p1 and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN885747/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I81a8793c1a118764df3ac97b67f5e088f56f6a20
2022-03-10fix(security): workaround for CVE-2022-23960Bipin Ravi
Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
2021-01-13Workaround for Cortex N1 erratum 1946160johpow01
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present starting from r0p0 but this workaround applies to revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
2020-11-30Add support for Neoverse-N2 CPUs.Javier Almansa Sobrino
Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
2020-09-10Workaround for Neoverse N1 erratum 1868343johpow01
Neoverse N1 erratum 1868343 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. SDEN can be found here: https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
2020-09-02lib: cpu: Check SCU presence in DSU before accessing DSU registersPramod Kumar
The DSU contains system control registers in the SCU and L3 logic to control the functionality of the cluster. If "DIRECT CONNECT" L3 memory system variant is used, there won't be any L3 cache, snoop filter, and SCU logic present hence no system control register will be present. Hence check SCU presence before accessing DSU register for DSU_936184 errata. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63
2020-07-23Revert workaround for Neoverse N1 erratum 1800710johpow01
This reverts commit 11af40b6308ac75c83e874129bb79bc3a58060bf, reversing changes made to 2afcf1d4b845272791b75c8285108c4dcd91e2b9. This errata workaround did not work as intended so we are reverting this change. In the future, when the corrected workaround is published in an SDEN, we will push a new workaround. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97
2020-06-25Workaround for Neoverse N1 erratum 1800710johpow01
Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6
2020-01-27Neovers N1: added support to update presence of External LLCManish Pandey
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
2020-01-22Prevent speculative execution past ERETAnthony Steinhauser
Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS: https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8 https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61 https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2 https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
2019-10-24Fix white space errors + remove #if definedlaurenw-arm
Fix a few white space errors and remove #if defined in workaround for N1 Errata 1542419. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I07ac5a2fd50cd63de53c06e3d0f8262871b62fad
2019-10-04Neoverse N1 Errata Workaround 1542419laurenw-arm
Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-19Fix for N1 1043202 Errata Workaroundlaurenw-arm
ISB instruction was removed from the N1 1043202 Errata Workaround [1], this fix is adding the ISB instruction back in. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I74eac7f6ad38991c36d423ad6aa44558033ad388
2019-07-02Removing redundant ISB instructionslauwal01
Replacing ISB instructions in each Errata workaround with a single ISB instruction before the RET in the reset handler. Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1275112lauwal01
Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1262888lauwal01
Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1262606lauwal01
Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1257314lauwal01
Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1220197lauwal01
Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1207823lauwal01
Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1165347lauwal01
Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1130799lauwal01
Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1073348lauwal01
Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-11DSU: Apply erratum 936184 for Neoverse N1/E1Louis Mayencourt
Change-Id: Idd08914bcb945ad6aa0621e594c95df88ee8f9c8 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-06-07Merge "Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703" ↵John Tsichritzis
into integration
2019-06-06Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703Andre Przywara
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-06-04Apply compile-time check for AArch64-only coresJohn Tsichritzis
Some cores support only AArch64 mode. In those cores, only a limited subset of the AArch32 system registers are implemented. Hence, if TF-A is supposed to run on AArch64-only cores, it must be compiled with CTX_INCLUDE_AARCH32_REGS=0. Currently, the default settings for compiling TF-A are with the AArch32 system registers included. So, if we compile TF-A the default way and attempt to run it on an AArch64-only core, we only get a runtime panic. Now a compile-time check has been added to ensure that this flag has the appropriate value when AArch64-only cores are included in the build. Change-Id: I298ec550037fafc9347baafb056926d149197d4c Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-14Disable speculative loads only if SSBS is supportedSami Mujawar
Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative loads (SSBS) is implemented, before disabling speculative loads. Change-Id: I7607c45ed2889260d22a94f6fd9af804520acf67 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2019-05-03Add compile-time errors for HW_ASSISTED_COHERENCY flagJohn Tsichritzis
This patch fixes this issue: https://github.com/ARM-software/tf-issues/issues/660 The introduced changes are the following: 1) Some cores implement cache coherency maintenance operation on the hardware level. For those cores, such as - but not only - the DynamIQ cores, it is mandatory that TF-A is compiled with the HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is unpredictable. To prevent this, compile time checks have been added and compilation errors are generated, if needed. 2) To enable this change for FVP, a logical separation has been done for the core libraries. A system cannot contain cores of both groups, i.e. cores that manage coherency on hardware and cores that don't do it. As such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the libraries only of the relevant cores. 3) The neoverse_e1.S file has been added to the FVP sources. Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-04-18Neoverse N1: Forces cacheable atomic to nearLouis Mayencourt
This patch forces all cacheable atomic instructions to be near, which improves performance in highly contended parallelized use-cases. Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-03-14Apply variant 4 mitigation for Neoverse N1John Tsichritzis
This patch applies the new MSR instruction to directly set the PSTATE.SSBS bit which controls speculative loads. This new instruction is available at Neoverse N1 core so it's utilised. Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19Rename Cortex-Ares to Neoverse N1John Tsichritzis
Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19Rename Cortex-Ares filenames to Neoverse N1John Tsichritzis
Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-23 08:00:35 +0000