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2023-08-24refactor(cpus): add Cortex-A57 errata framework informationBoyan Karatotev
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Ic435b8d42639454fabb587ead44f646f7285cc40
2023-08-10fix(cpus): flush L2 cache for Cortex-A7/12/15/17Stephan Gerhold
Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an (optional) integrated L2 cache that might need to be flushed if the whole cluster is powered down. However, unlike Cortex-A53 there is currently no L2 cache flush in the cluster_pwr_dwn implementation for some reason. This causes problems if there is unwritten data left in the L2 cache during a cluster power off. Fix this by adding the L2 cache flush similar to cortex_a53.S. Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-08-08chore: update to use Arm word across TF-AGovindraj Raja
Align entire TF-A to use Arm in copyright header. Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-08-05Merge changes from topic "sm/errata_refactor" into integrationBipin Ravi
* changes: refactor(cpus): convert Cortex-A15 to use the errata framework refactor(cpus): convert the Cortex-X3 to use the cpu helpers refactor(cpus): convert Cortex-X3 to use the errata framework refactor(cpus): reorder Cortex-X3 errata by ascending order refactor(cpus): convert the Cortex-A73 to use the cpu helpers refactor(cpus): convert Cortex-A73 to use the errata framework refactor(cpus): reorder Cortex-A73 errata by ascending order refactor(cpus): convert the Cortex-A35 to use the cpu helpers refactor(cpus): convert Cortex-A35 to use the errata framework
2023-08-04refactor(cpus): convert Cortex-A15 to use the errata frameworkSona Mathew
Change-Id: I569b0da3ed5b81b4b6e9a7820d32684376a190a9 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
2023-08-04refactor(cpus): convert the Cortex-A5 to use the errata frameworkBoyan Karatotev
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I8214fdff2c528ccfa64a366ee1f3bc04d52a0bf8
2023-08-03refactor(cpus): use cpu errata wrappers Cortex-A12 aarch32 cpuGovindraj Raja
Adapt to use errata frame-work cpu macro helpers for Cortex-A12 aarch32 cpu. Testing: - Manual comparison of disassembly with and without the patch. - Compile testing. Change-Id: I9bad7f1e3d87419c0451b5d46edf0c406d31a84d Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-08-03refactor(cpus): use cpu errata wrappers Cortex-A7 and A9 aarch32 cpusGovindraj Raja
Adapt to use errata frame-work cpu macro helpers for following cpu's: - Cortex-A7 - Cortex-A9 Testing: - Manual comparison of disassembly with and without the patch. - Compile testing. Change-Id: I88eb90d7fd0e82fc4bfc9d1aee947f0c820e1222 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-07-27fix(cpus): fix minor issue seen with a9 cpuGovindraj Raja
fix typo in a9_794073 report errata. Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> Change-Id: Iace9f7fd18af529823488b6b6cb79e6bc13b9d4d
2023-07-28Merge changes from topic "hm/errata-fw" into integrationBipin Ravi
* changes: refactor(cpus): add Cortex-A17 errata framework information fix(fvp): resolve broken workaround reference
2023-07-27refactor(cpus): add Cortex-A53 errata framework informationJayanth Dodderi Chidanand
Change-Id: I3518847728fa17baa423cfef66694895a39ee888 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2023-07-20refactor(cpus): add Cortex-A17 errata framework informationHarrison Mutai
Change-Id: I19d096edf47c1a9f47e79e9bb95984ce2102fad4 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-07-20fix(fvp): resolve broken workaround referenceHarrison Mutai
The workaround for CVE 2015-5715 was renamed many years ago, however, Cortex-A17 and A9 didn't see this change. Change-Id: I553c8b09543263bca2a34eaef670af0424999cfe Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-06-27refactor(cpus): add Cortex-A72 errata informationMaksims Svecovs
* adds add_erratum_etnry for all described erratas. * replaces errata_report function with errata_report_shim to report errata automatically Change-Id: I7e3315d5cc77b77c328fff7f3988ec588b8f88b9 Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
2023-06-26refactor(cpus): add Cortex-A32 errata framework informationKathleen Capella
Replace errata_report with errata_report_shim. Signed-off-by: Kathleen Capella <kathleen.capella@arm.com> Change-Id: I5a43b0985f070f887474120eb8f5f7c01ba4af5f
2023-05-30refactor(cpus): convert print_errata_status to CBoyan Karatotev
The function is called in a fully initialised C environment and calls into other C functions. The Aarch differences are minimal and are hidden by the pre-existing headers. Converting it results into cleaner code that is the same across both Aarch64 and Aarch32. To avoid having to do very ugly pointer arithmetic, define a C struct for the cpu_ops for both Aarch64 and Aarch32. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Idc07c4064e03143c88a4a0e2d10ceda70ba19a50
2023-05-30refactor(cpus): move cpu_ops field defines to a headerBoyan Karatotev
The cpu_macros.S file is loaded with lots of definitions for the cpu_ops structure. However, since they are defined as .equ directives they are inaccessible for C code. Convert them to #defines, put them into order, refactor them for readability, and extract them to a separate file to make this possible. This has the benefit of removing some Aarch differences and a lot of duplicate code. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I72861794b6c9131285a9297d5918822ed718b228
2023-03-15refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3Arvind Ram Prakash
BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
2022-05-05fix(security): report CVE 2022 23960 missing for aarch32 A57 and A72John Powell
Since there is no product deployed running EL3 in AArch32 mode for Cortex-A57 and Cortex-A72, report the workaround for CVE 2022 23960 as missing on these cores. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I14d202c1179707257086ad0c4795c397e566b3e6
2022-04-28fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960John Powell
Cortex-A15 does not support FEAT_CSV2 so the existing workaround for Spectre V2 is sufficient to mitigate against Spectre BHB attacks, however the code needed to be updated to work with the new build flag. Also, some code was refactored several years ago and not updated in the Cortex-A15 library file so this patch fixes that as well. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I768c88a38c561c91019b038ac6c22b291955f18e
2021-02-23lib: cpus: aarch32: sanity check pointers before useYann Gautier
This is the AARCH32 update of patch [1]. [1] 601e3ed209eb ("lib: cpus: sanity check pointers before use") Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I43dbe00a5802a7e1c6f877e22d1c66ec8275c6fa
2019-04-12Cortex A9:errata 794073 workaroundJoel Hutton
On Cortex A9 an errata can cause the processor to violate the rules for speculative fetches when the MMU is off but branch prediction has not been disabled. The workaround for this is to execute an Invalidate Entire Branch Prediction Array (BPIALL) followed by a DSB. see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf for more details. Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93 Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
2019-03-13Cortex-A17: Implement workaround for errata 852423Ambroise Vincent
Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13Cortex-A17: Implement workaround for errata 852421Ambroise Vincent
Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13Cortex-A15: Implement workaround for errata 827671Ambroise Vincent
This erratum can only be worked around on revisions >= r3p0 because the register that needs to be accessed only exists in those revisions[1]. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13Cortex-A15: Implement workaround for errata 816470Ambroise Vincent
Change-Id: I9755252725be25bfd0147839d7df56888424ff84 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-08Fixup register handling in aarch32 reset_handlerHeiko Stuebner
The BL handover interface stores the bootloader arguments in registers r9-r12, so when the reset_handler stores the lr pointer in r10 it clobers one of the arguments. Adapt to use r8 and adapt the comment about registers allowed to clober. I've checked aarch32 reset_handlers and none seem to use higher registers as far as I can tell. Fixes: a6f340fe58b9 ("Introduce the new BL handover interface") Cc: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-01Merge pull request #1751 from vwadekar/tegra-scatter-file-supportAntonio Niño Díaz
Tegra scatter file support
2019-02-28Cortex-A53: Workarounds for 819472, 824069 and 827319Ambroise Vincent
The workarounds for these errata are so closely related that it is better to only have one patch to make it easier to understand. Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28Cortex-A57: Implement workaround for erratum 817169Ambroise Vincent
Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28Cortex-A57: Implement workaround for erratum 814670Ambroise Vincent
Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-27Tegra: Support for scatterfile for the BL31 imageVarun Wadekar
This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-29Make errata reporting mandatory for CPU filesSoby Mathew
Previously the errata reporting was optional for CPU operation files and this was achieved by making use of weak reference to resolve to 0 if the symbol is not defined. This is error prone when adding new CPU operation files and weak references are problematic when fixing up dynamic relocations. Hence this patch removes the weak reference and makes it mandatory for the CPU operation files to define the errata reporting function. Change-Id: I8af192e19b85b7cd8c7579e52f8f05a4294e5396 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-05-23aarch32: Implement static workaround for CVE-2018-3639Dimitris Papastamos
Implement static mitigation for CVE-2018-3639 on Cortex A57 and A72. Change-Id: I83409a16238729b84142b19e258c23737cc1ddc3 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-22Fixup AArch32 errata printing frameworkSoby Mathew
The AArch32 assembly implementation of `print_errata_status` did not save a register which was getting clobbered by a `get_cpu_ops_ptr`. This patch fixes that. Change-Id: Id0711e46b7c685a18a10328d4b513e952a5d860b Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-01-25Merge pull request #1228 from dp-arm/dp/cve_2017_5715davidcunado-arm
Workarounds for CVE-2017-5715 on A9/A15 and A17 + serial console reporting
2018-01-20Merge pull request #1229 from ↵davidcunado-arm
manojkumar-arm/manojkumar-arm/ca72-aarch32-reset-fix lib/cpus: fix branching in reset function for cortex-a72 AARCH32 mode
2018-01-19lib/cpus: fix branching in reset function for cortex-a72 AARCH32 modeManoj Kumar
In AARCH32 mode, cortex_a72_reset_func branches to address in lr register instead of r5 register. This leads to linux boot failure of Cortex-A72 cores in AARCH32 mode on Juno-R2 board. This patch fixes the branching of cortex_a72_reset_func to r5 register as in cortex_a57_reset_func implementation. Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
2018-01-18Workaround for CVE-2017-5715 for Cortex A9, A15 and A17Dimitris Papastamos
A per-cpu vbar is installed that implements the workaround by invalidating the branch target buffer (BTB) directly in the case of A9 and A17 and indirectly by invalidating the icache in the case of A15. For Cortex A57 and A72 there is currently no workaround implemented when EL3 is in AArch32 mode so report it as missing. For other vulnerable CPUs (e.g. Cortex A73 and Cortex A75), there are no changes since there is currently no upstream AArch32 EL3 support for these CPUs. Change-Id: Ib42c6ef0b3c9ff2878a9e53839de497ff736258f Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-18bl2-el3: Add BL2_EL3 imageRoberto Vargas
This patch enables BL2 to execute at the highest exception level without any dependancy on TF BL1. This enables platforms which already have a non-TF Boot ROM to directly load and execute BL2 and subsequent BL stages without need for BL1. This is not currently possible because BL2 executes at S-EL1 and cannot jump straight to EL3. Change-Id: Ief1efca4598560b1b8c8e61fbe26d1f44e929d69 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2017-12-04Merge pull request #1168 from matt2048/masterdavidcunado-arm
Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONS
2017-11-23Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONSMatt Ma
This patch replaces the macro ASM_ASSERTION with the macro ENABLE_ASSERTIONS in ARM Cortex-A53/57/72 MPCore Processor related files. There is build error when ASM_ASSERTION is set to 1 and ENABLE_ASSERTIONS is set to 0 because function asm_assert in common/aarch32/debug.S is defined in the macro ENABLE_ASSERTIONS but is called with the macro ASM_ASSERTION. There is also the indication to use ENABLE_ASSERTIONS but not ASM_ASSERTION in the Makefile. Signed-off-by: Matt Ma <matt.ma@spreadtrum.com>
2017-11-08ARMv7: introduce Cortex-A12Etienne Carriere
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-11-08ARMv7: introduce Cortex-A17Etienne Carriere
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-11-08ARMv7: introduce Cortex-A7Etienne Carriere
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-11-08ARMv7: introduce Cortex-A5Etienne Carriere
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-11-08ARMv7: introduce Cortex-A9Etienne Carriere
As Cortex-A9 needs to manually enable program flow prediction, do not reset SCTLR[Z] at entry. Platform should enable it only once MMU is enabled. Change-Id: I34e1ee2da73221903f7767f23bc6fc10ad01e3de Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-11-08ARMv7: introduce Cortex-A15Etienne Carriere
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-09-07Cortex-A72: Implement workaround for erratum 859971Eleanor Bonnici
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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