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2023-11-02fix(cpus): workaround for Cortex-A710 erratum 2742423Bipin Ravi
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all revisions <= r2p1 and is still open. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-11-02fix(cpus): workaround for Neoverse N2 erratum 2340933Bipin Ravi
Neoverse N2 erratum 2340933 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR5_EL1[61] to 1. SDEN documentation: https://developer.arm.com/documentation/SDEN-1982442/latest Change-Id: I121add0dd35072c53392d33f049d893a5ff6354f Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-11-02fix(cpus): workaround for Neoverse N2 erratum 2346952Bipin Ravi
Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all revisions <= r0p2 and is fixed in r0p3. The workaround is to set L2 TQ size statically to it's full size. SDEN documentation: https://developer.arm.com/documentation/SDEN-1982442/latest Change-Id: I03c3cf1f951fbc906fdebcb99a523c5ac8ba055d Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2023-11-01Merge changes from topic "fw-caps" into integrationMadhukar Pappireddy
* changes: feat(ti): query firmware for suspend capability feat(ti): add TI-SCI query firmware capabilities command support feat(ti): remove extra core counts in cluster 2 and 3
2023-11-01Merge "fix(tegra): return correct error code for plat_core_pos_by_mpidr" ↵Manish Pandey
into integration
2023-11-01fix(tegra): return correct error code for plat_core_pos_by_mpidrManish Pandey
The error code for plat_core_pos_by_mpidr() for an invalid mpidr should be -1 as mandated by portig guide, but for tegra t186 return value is PSCI_E_NOT_PRESENT (-7) even though the comment at top of function says that it should return -1. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I2b69bc1a56f7966f21b2a3c89c515ebde41e3eb8
2023-11-01Merge changes from topic "hst/cs1k-add-gpt-support" into integrationManish V Badarkhe
* changes: feat(bl2): add gpt support fix(corstone-1000): modify boot device dependencies fix(corstone-1000): removing the signature area
2023-10-31Merge "feat(cpufeat): add memory retention bit define for CLUSTERPWRDN" into ↵Madhukar Pappireddy
integration
2023-10-31feat(bl2): add gpt supportHarsimran Singh Tungal
This includes initialization of the partition with the GPT_IMAGE_ID. Change-Id: I51b09d82ff40207369d76011556f40169196af22 Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com> Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
2023-10-31fix(corstone-1000): modify boot device dependenciesHarsimran Singh Tungal
Modify boot device dependencies and remove the one's which are not needed. Change-Id: I71cd60558ab4bb5162afefad4f00d631c2308e72 Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com> Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
2023-10-31Merge "refactor(cm): move EL3 registers to global context" into integrationManish Pandey
2023-10-31Merge "fix(build): remove handling of mandatory options" into integrationManish Pandey
2023-10-31Merge changes from topic "hm/mpam" into integrationManish Pandey
* changes: fix(build): convert tabs and ifdef comparisons fix(build): disable ENABLE_FEAT_MPAM for Aarch32
2023-10-31fix(build): convert tabs and ifdef comparisonsHarrison Mutai
Make interprets lines prefixed with the tab characters as recipes (commands to run in the shell). Convert the use of ifdef as this incorrectly interprets when a flag is disabled i.e. `ENABLE_FEAT_MPAM=0`. Change-Id: I5173d18a20ef0e3ffc32f0ffb1e70dc30aa4c4a9 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-10-31Merge "refactor(fvp): do not use RSS platform token and attestation key ↵Manish V Badarkhe
APIs" into integration
2023-10-31fix(build): disable ENABLE_FEAT_MPAM for Aarch32Harrison Mutai
Disable FEAT_MPAM support for Aarch32 as it is not supported, following [1]. ENABLE_FEAT_MPAM is set to 2 by default for Aarch64 in arch_features.mk, eliminating the need for duplication in the platform makefile. [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/23710 Change-Id: I1c8b6844254e00e6372900f1c87f995f292ae65c Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-10-31fix(corstone-1000): removing the signature areaHarsimran Singh Tungal
The TF-M on the secure enclave side takes care of boot bank selection for our platform. The TF-A doesn't require to manage the boot bank, so, removing the boot bank selection. TF-A doesn't expect the signature area so removed it from FIP partition Change-Id: I298dd51fa068534c299c66b0e4c353819ea12a26 Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com> Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
2023-10-31Merge changes from topic "hm/post-image" into integrationManish Pandey
* changes: refactor(fvp): move image handling into generic procedure refactor(bl2): make post image handling platform-specific
2023-10-31refactor(cm): move EL3 registers to global contextElizabeth Ho
Currently, EL3 context registers are duplicated per-world per-cpu. Some registers have the same value across all CPUs, so this patch moves these registers out into a per-world context to reduce memory usage. Change-Id: I91294e3d5f4af21a58c23599af2bdbd2a747c54a Signed-off-by: Elizabeth Ho <elizabeth.ho@arm.com> Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2023-10-31Merge "feat(rmm): update RMI VERSION command as per EAC5" into integrationSoby Mathew
2023-10-30feat(rmm): update RMI VERSION command as per EAC5Shruti Gupta
This patch adds necessary support for RMI_VERSION command. This patch sets RMI version numbers to 1.0 as per RMM Specification 1.0-eac5. Change-Id: If7f88d5b5efa58716752488108fa110fc71ae836 Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
2023-10-30Merge "fix(versal): type cast addresses to fix integer overflow" into ↵Joanna Farley
integration
2023-10-30fix(build): remove handling of mandatory optionsGovindraj Raja
With commit@f5211420b(refactor(cpufeat): refactor arch feature build options all mandatory options are enabled with 'make_helpers/arch_features.mk' so avoid enabling of mandatory features in platform makefile. Use correct Arch Major/Minor to get all the mandatory features enabled by default. Change-Id: Ia214aa75dc9caea949f697ecafb1ef1812c6d899 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-30Merge changes from topic "gr/build_refactor" into integrationManish Pandey
* changes: build(refactor): avoid ifdef comparison refactor(build): avoid using values for comparison refactor(build): reorder arch features handling build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINOR refactor(build): reorder platform Makefile evaluation
2023-10-30build(refactor): avoid ifdef comparisonGovindraj Raja
During build 'ENABLE_SPE_FOR_NS=0' is a valid build option however using ifdef would incorrectly translate this as enabled. Change-Id: I1c516fb68f6e382bb83c578e499cbb86869d9eca Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-30refactor(build): avoid using values for comparisonGovindraj Raja
With changes to refactor to use first platform makefiles then parse arch_features.mk file 'ENABLE_RME' will be initialised only when we define during build or at arch_features.mk thus making comparison of 'ENABLE_RME' to '0' incorrect. So keep BRBE disabled when RME is enabled at main makefile level. Change-Id: I7e3d99eb444678d63585bd5971ada627cfc4fcc9 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-30refactor(build): reorder arch features handlingGovindraj Raja
With commit@f5211420b(refactor(cpufeat): refactor arch feature build options all mandatory options are enabled with 'make_helpers/arch_features.mk' However the commit makes it impossible for enabling of mandatory features through command line and platform make files, So re-order handling of mandatory features in 'make_helpers/arch_features.mk' Use below order to enable mandatory features. 1.) first enable mandatory features by arch major/minor 2.) check if features were not earlier defined in platform makefile or through cmdline if defined earlier don't initialise them to '0' but retain their values from prior initialisation. Change-Id: Icea3180c9dda0cd6e0b59316add9f3290ae51972 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-30build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINORGovindraj Raja
n1sdp based out of Arm Neoverse N1 Core uses Arm®v8.2‑A extensions so set ARM_ARCH_MAJOR.ARM_ARCH_MINOR for n1sdp platform to 8.2 Change-Id: Ib70c6be5e12817961430870d50fb1b0efca32df2 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-30refactor(build): reorder platform Makefile evaluationGovindraj Raja
Commit(f5211420b refactor(cpufeat): refactor arch feature build options) ensures mandatory arch features are enabled based on ARM_ARCH_MAJOR and ARM_ARCH_MINOR, which would be expected to be provided from platform makefile. However it missed ensuring platform makefile is included before parsing and enabling any mandatory arch features. Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> Change-Id: Ia0ccb7d73b2d24c87d3d235babed4704230bec28
2023-10-30Merge changes from topic "mb/psa-crypto-ecdsa" into integrationLauren Wehrmeister
* changes: docs: mark PSA_CRYPTO as an experimental feature feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation feat(mbedtls-psa): mbedTLS PSA Crypto with ECDSA
2023-10-30fix(versal): type cast addresses to fix integer overflowPrasad Kummari
Typecast the base and size arguments for build time as unsigned integers and the limit derived from these two as an unsigned long to prevent size integer overflow issues during the build. Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Change-Id: Iefc148e0091e8c8a4ca505691036c79528a558a4
2023-10-30refactor(fvp): move image handling into generic procedureHarrison Mutai
Post image handling of the HW_CONFIG is out-of-scope for `plat_get_next_bl_params`. Move parts of the code responsible for post processing of loaded images into `bl2_plat_handle_post_image_load` for code reusability and maintainability. Change-Id: I476b3d306ebcd4529f5e542ba1063e144920bb5f Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-10-30refactor(bl2): make post image handling platform-specificHarrison Mutai
In certain instances a platform may need to make modifications to an image after it has been loaded by BL2. The existing common implementation is a thin wrapper for a more generic arm post image handler. To enable platforms to make changes to images when they're loaded, move this into platform code. Change-Id: I44025391056adb2d8a8eb4ea5984257b02027181 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-10-30Merge "fix(ast2700): add device mapping for coherent memory" into integrationManish V Badarkhe
2023-10-30fix(ast2700): add device mapping for coherent memoryChia-Wei Wang
The coherent memory should be mapped as Device nGnRnE. This fix adds the missing MMU attributes for coherent memory if enabled. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Change-Id: I90b8de167c48f03392c9740f88f4b1e7b073a82d
2023-10-27Merge changes from topic "mb/cov-fix" into integrationLauren Wehrmeister
* changes: fix(tbbr): guard defines under MBEDTLS_CONFIG_FILE refactor(tbbr): enforce compile-time error for invalid algorithm selection
2023-10-27feat(ti): query firmware for suspend capabilityAndrew Davis
Instead of hardcoding this at build time we can ask the firmware if suspend is supported and if not disable accordingly. Then remove compile- time ifdefs. Signed-off-by: Andrew Davis <afd@ti.com> Change-Id: Ib966c04c0bdb79a82e8d890cec5e65d883acd6e3
2023-10-27feat(ti): add TI-SCI query firmware capabilities command supportAndrew Davis
This TISCI API is used to retrieve the firmware capabilities of the currently running system-firmware. Signed-off-by: Andrew Davis <afd@ti.com> Change-Id: I55402dcf876e997eb21bb1f31c725e167c507c47
2023-10-27feat(ti): remove extra core counts in cluster 2 and 3Andrew Davis
No K3 SoC supported by this TARGET_BOARD has any cluster 2 or 3 cores. Remove these to save some memory. Signed-off-by: Andrew Davis <afd@ti.com> Change-Id: I27868a2f3aac25fa0fdec56847e273d88f0d9a87
2023-10-27Merge changes from topic "gpt_updates" into integrationSandrine Bailleux (on vacation)
* changes: refactor(arm): use gpt_partition_init feat(partition): add interface to init gpt refactor(partition): convert warn to verbose feat(partition): add support to use backup GPT header refactor(partition): get GPT header location from MBR feat(arm): add IO policy to use backup gpt header feat(tbbr): add image id for backup GPT
2023-10-27Merge "feat(cpus): add support for Travis CPU" into integrationMadhukar Pappireddy
2023-10-27Merge "fix(ti): align static device region addresses to reduce MMU table ↵Madhukar Pappireddy
count" into integration
2023-10-27Merge "feat(handoff): port BL31-BL33 interface to fw handoff framework" into ↵Manish Pandey
integration
2023-10-27refactor(arm): use gpt_partition_initGovindraj Raja
Current interface partition_init accepts GPT image id and parses the GPT image but doesn't return any error on failure. So use gpt_partition_init which implicitly initialises with GPT image ID and returns a value. Change-Id: I63280aa672388f1f8d9dc377ae13002c9f861f03 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-27feat(partition): add interface to init gptGovindraj Raja
Current interface 'partition_init' accepts parameter image_id and returns no value. But the entire partition driver is build only to parse and handle GPT partitions, so add new interface gpt_partition_init which would return failure to platform code if it fails to parse the image. Change-Id: Iaf574d2ad01a15d0723c1475290c31dc4a078835 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-27refactor(partition): convert warn to verboseGovindraj Raja
Convert all warn messages to verbose messages. As most warning are needed during debug only and and won't increase the binary size by default. Change-Id: Icc5d5157f13507ccbc34675c20357117cad98255 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-27feat(partition): add support to use backup GPT headerGovindraj Raja
Currently we just use primary GPT header which is located in second entry after MBR header, but if this block is corrupted or CRC mismatch occurs we could try to use the backup GPT header located at LBAn and GPT entries following this from LBA-33. Add suitable warning messages before returning any errors to identify the cause of issue. Change-Id: I0018ae9eafbacb683a18784d2c8bd917c70f50e1 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-27refactor(partition): get GPT header location from MBRGovindraj Raja
GPT header is located in first LBA after MBR entry and mbr header has details of beginning of first entry, so use mbr header entry first_lba data to locate GPT header rather than GPT_HEADER_OFFSET. GPT header size is available in gpt_header, so use that rather than using DEFAULT_GPT_HEADER_SIZE. The location of GPT entries is available once we parse gpt_header and is available as partitiona_lba use that to load gpt_entries rather than GPT_ENTRY_OFFSET. Change-Id: I3c11f8cc9d4b0b1778a37fe342fb845ea4a4eff1 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-27feat(arm): add IO policy to use backup gpt headerGovindraj Raja
Add a IO block spec to use GPT backup header if primary fails. Currently we use only the primary gpt header which is in the second block(LBA-1) after the MBR block(LBA-0) so we restrict IO access to primary gpt header and its entries. But we plan to use backup GPT which is the last block of the partition (LBA-n) in case our primary GPT header fails verification or is corrupted. Offset and length of the block spec will be updated runtime from partition driver after parsing MBR data. Change-Id: Id1d49841d6f4cbcc3248af19faf2fbd8e24a8ba1 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-10-27feat(tbbr): add image id for backup GPTGovindraj Raja
Add image identifier to access backup-GPT header and entry, when we fail to get primary GPT header. Currently we use only the primary gpt header, But we plan to use backup GPT header in case our primary GPT header fails verification or is corrupted. Change-Id: I12eedd5d2a5cda21c64254d461d09d400d4edb30 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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