diff options
Diffstat (limited to 'lib/el3_runtime')
| -rw-r--r-- | lib/el3_runtime/aarch64/context.S | 37 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 59 |
2 files changed, 40 insertions, 56 deletions
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 769117163..0f2dfeb77 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -17,10 +17,6 @@ .global el2_sysregs_context_save_mte .global el2_sysregs_context_restore_mte #endif /* CTX_INCLUDE_MTE_REGS */ -#if RAS_EXTENSION - .global el2_sysregs_context_save_ras - .global el2_sysregs_context_restore_ras -#endif /* RAS_EXTENSION */ #endif /* CTX_INCLUDE_EL2_REGS */ .global el1_sysregs_context_save @@ -210,30 +206,6 @@ func el2_sysregs_context_restore_mte endfunc el2_sysregs_context_restore_mte #endif /* CTX_INCLUDE_MTE_REGS */ -#if RAS_EXTENSION -func el2_sysregs_context_save_ras - /* - * VDISR_EL2 and VSESR_EL2 registers are saved only when - * FEAT_RAS is supported. - */ - mrs x11, vdisr_el2 - mrs x12, vsesr_el2 - stp x11, x12, [x0, #CTX_VDISR_EL2] - ret -endfunc el2_sysregs_context_save_ras - -func el2_sysregs_context_restore_ras - /* - * VDISR_EL2 and VSESR_EL2 registers are restored only when FEAT_RAS - * is supported. - */ - ldp x11, x12, [x0, #CTX_VDISR_EL2] - msr vdisr_el2, x11 - msr vsesr_el2, x12 - ret -endfunc el2_sysregs_context_restore_ras -#endif /* RAS_EXTENSION */ - #endif /* CTX_INCLUDE_EL2_REGS */ /* ------------------------------------------------------------------ @@ -855,7 +827,12 @@ sve_not_enabled: 1: #endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */ -#if IMAGE_BL31 && RAS_EXTENSION +/* + * This is a hot path, so we don't want to do some actual FEAT_RAS runtime + * detection here. The "esb" is a cheaper variant, so using "dsb" in the + * ENABLE_FEAT_RAS==2 case is not ideal, but won't hurt. + */ +#if IMAGE_BL31 && ENABLE_FEAT_RAS == 1 /* ---------------------------------------------------------- * Issue Error Synchronization Barrier to synchronize SErrors * before exiting EL3. We're running with EAs unmasked, so @@ -866,7 +843,7 @@ sve_not_enabled: esb #else dsb sy -#endif /* IMAGE_BL31 && RAS_EXTENSION */ +#endif /* IMAGE_BL31 && ENABLE_FEAT_RAS */ /* ---------------------------------------------------------- * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index b69c7ccd6..3760b8f13 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -517,12 +517,13 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) amu_enable(el2_unused, ctx); } - /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ + /* Enable SVE and FPU/SIMD */ + if (is_feat_sve_supported()) { + sve_enable(ctx); + } + if (is_feat_sme_supported()) { sme_enable(ctx); - } else if (is_feat_sve_supported()) { - /* Enable SVE and FPU/SIMD for non-secure world. */ - sve_enable(ctx); } if (is_feat_mpam_supported()) { @@ -553,22 +554,7 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) static void manage_extensions_secure(cpu_context_t *ctx) { #if IMAGE_BL31 - - if (is_feat_sme_supported()) { - if (ENABLE_SME_FOR_SWD) { - /* - * Enable SME, SVE, FPU/SIMD in secure context, secure manager - * must ensure SME, SVE, and FPU/SIMD context properly managed. - */ - sme_enable(ctx); - } else { - /* - * Disable SME, SVE, FPU/SIMD in secure context so non-secure - * world can safely use the associated registers. - */ - sme_disable(ctx); - } - } else if (is_feat_sve_supported()) { + if (is_feat_sve_supported()) { if (ENABLE_SVE_FOR_SWD) { /* * Enable SVE and FPU in secure context, secure manager must @@ -585,6 +571,21 @@ static void manage_extensions_secure(cpu_context_t *ctx) } } + if (is_feat_sme_supported()) { + if (ENABLE_SME_FOR_SWD) { + /* + * Enable SME, SVE, FPU/SIMD in secure context, secure manager + * must ensure SME, SVE, and FPU/SIMD context properly managed. + */ + sme_enable(ctx); + } else { + /* + * Disable SME, SVE, FPU/SIMD in secure context so non-secure + * world can safely use the associated registers. + */ + sme_disable(ctx); + } + } #endif /* IMAGE_BL31 */ } @@ -1012,9 +1013,13 @@ void cm_el2_sysregs_context_save(uint32_t security_state) write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, read_ttbr1_el2()); } -#if RAS_EXTENSION - el2_sysregs_context_save_ras(el2_sysregs_ctx); -#endif + + if (is_feat_ras_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, + read_vdisr_el2()); + write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, + read_vsesr_el2()); + } if (is_feat_nv2_supported()) { write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, @@ -1095,9 +1100,11 @@ void cm_el2_sysregs_context_restore(uint32_t security_state) write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); } -#if RAS_EXTENSION - el2_sysregs_context_restore_ras(el2_sysregs_ctx); -#endif + + if (is_feat_ras_supported()) { + write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); + write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); + } if (is_feat_nv2_supported()) { write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); |