diff options
| -rw-r--r-- | Makefile | 5 | ||||
| -rw-r--r-- | bl1/bl1.ld.S | 14 | ||||
| -rw-r--r-- | bl2/bl2.ld.S | 12 | ||||
| -rw-r--r-- | bl2/bl2_el3.ld.S | 12 | ||||
| -rw-r--r-- | bl2u/bl2u.ld.S | 12 | ||||
| -rw-r--r-- | bl31/bl31.ld.S | 12 |
6 files changed, 34 insertions, 33 deletions
@@ -285,8 +285,9 @@ CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \ ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \ -ffreestanding -Wa,--fatal-warnings TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ - -ffreestanding -fno-builtin -std=gnu99 \ - -Os -ffunction-sections -fdata-sections + -ffunction-sections -fdata-sections \ + -ffreestanding -fno-builtin -fno-common \ + -Os -std=gnu99 ifeq (${SANITIZE_UB},on) TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index c4f6b99fc..877af8e01 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl1_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -44,7 +44,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -72,8 +72,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl1_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -114,7 +114,7 @@ SECTIONS */ .data . : ALIGN(16) { __DATA_RAM_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_RAM_END__ = .; } >RAM AT>ROM @@ -131,7 +131,7 @@ SECTIONS */ .bss : ALIGN(16) { __BSS_START__ = .; - *(.bss*) + *(SORT_BY_ALIGNMENT(.bss*)) *(COMMON) __BSS_END__ = .; } >RAM diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index 30cdf7d78..6230562ed 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl2_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -44,7 +44,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -59,8 +59,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl2_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -93,7 +93,7 @@ SECTIONS */ .data . : { __DATA_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_END__ = .; } >RAM diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S index 82b51a862..dc398eb02 100644 --- a/bl2/bl2_el3.ld.S +++ b/bl2/bl2_el3.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,7 +44,7 @@ SECTIONS *bl2_el3_entrypoint.o(.text*) *(.text.asm.*) __TEXT_RESIDENT_END__ = .; - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -52,7 +52,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -82,8 +82,8 @@ SECTIONS *bl2_el3_entrypoint.o(.text*) *(.text.asm.*) __TEXT_RESIDENT_END__ = .; - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* * Ensure 8-byte alignment for cpu_ops so that its fields are also @@ -135,7 +135,7 @@ SECTIONS */ .data . : { __DATA_RAM_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_RAM_END__ = .; } >RAM AT>ROM diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S index 8d4984fbf..8d257cee9 100644 --- a/bl2u/bl2u.ld.S +++ b/bl2u/bl2u.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl2u_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -44,7 +44,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; } >RAM @@ -52,8 +52,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl2u_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) *(.vectors) __RO_END_UNALIGNED__ = .; @@ -80,7 +80,7 @@ SECTIONS */ .data . : { __DATA_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_END__ = .; } >RAM diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index c7d587cb0..708ee329f 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -33,7 +33,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl31_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -41,7 +41,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -87,8 +87,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl31_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -179,7 +179,7 @@ SECTIONS */ .data . : { __DATA_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_END__ = .; } >RAM @@ -211,7 +211,7 @@ SECTIONS */ .bss (NOLOAD) : ALIGN(16) { __BSS_START__ = .; - *(.bss*) + *(SORT_BY_ALIGNMENT(.bss*)) *(COMMON) #if !USE_COHERENT_MEM /* |