diff options
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 4 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_x3.h | 9 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_x3.S | 7 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 5 | ||||
| -rw-r--r-- | services/std_svc/errata_abi/errata_abi_main.c | 9 |
5 files changed, 30 insertions, 4 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index bf0455809..ad05a505a 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -726,6 +726,10 @@ For Cortex-X2, the following errata build flags are defined : For Cortex-X3, the following errata build flags are defined : +- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3 + CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of + the CPU and is still open. + - ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it is fixed in r1p1. diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h index e64873408..04548eae4 100644 --- a/include/lib/cpus/aarch64/cortex_x3.h +++ b/include/lib/cpus/aarch64/cortex_x3.h @@ -38,4 +38,13 @@ #define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) #define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) +/******************************************************************************* + * CPU Extended Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5 + +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) + #endif /* CORTEX_X3_H */ diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 98d148e2e..0cb3b976b 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -26,6 +26,13 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 #endif /* WORKAROUND_CVE_2022_23960 */ +workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 + sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ + CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH +workaround_reset_end cortex_x3, ERRATUM(2070301) + +check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) + workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 77cc41e03..e12795f81 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -734,6 +734,11 @@ CPU_FLAG_LIST += ERRATA_X2_2701952 # still open. CPU_FLAG_LIST += ERRATA_X2_2768515 +# Flag to apply erratum 2070301 workaround on reset. This erratum applies +# to revisions r0p0, r1p0, r1p1 and r1p2 of the Cortex-X3 cpu and is +# still open. +CPU_FLAG_LIST += ERRATA_X3_2070301 + # Flag to apply erratum 2313909 workaround on powerdown. This erratum applies # to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1. CPU_FLAG_LIST += ERRATA_X3_2313909 diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c index ca6639698..c0a089b14 100644 --- a/services/std_svc/errata_abi/errata_abi_main.c +++ b/services/std_svc/errata_abi/errata_abi_main.c @@ -428,10 +428,11 @@ struct em_cpu_list cpu_list[] = { { .cpu_partnumber = CORTEX_X3_MIDR, .cpu_errata_list = { - [0] = {2313909, 0x00, 0x10, ERRATA_X3_2313909}, - [1] = {2615812, 0x00, 0x11, ERRATA_X3_2615812}, - [2] = {2742421, 0x00, 0x11, ERRATA_X3_2742421}, - [3 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [0] = {2070301, 0x00, 0x12, ERRATA_X3_2070301}, + [1] = {2313909, 0x00, 0x10, ERRATA_X3_2313909}, + [2] = {2615812, 0x00, 0x11, ERRATA_X3_2615812}, + [3] = {2742421, 0x00, 0x11, ERRATA_X3_2742421}, + [4 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* CORTEX_X3_H_INC */ |