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-rw-r--r--plat/xilinx/versal_net/bl31_versal_net_setup.c2
-rw-r--r--plat/xilinx/versal_net/include/versal_net_def.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index aa60bbfcc..a70095d40 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -106,7 +106,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/* Initialize the console to provide early debug support */
rc = console_pl011_register(UART_BASE, uart_clock,
- UART_BAUDATE,
+ UART_BAUDRATE,
&versal_net_runtime_console);
if (rc == 0) {
panic();
diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index c2422637d..a53cad955 100644
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -135,7 +135,7 @@
#define VERSAL_NET_UART0_BASE U(0xF1920000)
#define VERSAL_NET_UART1_BASE U(0xF1930000)
-#define UART_BAUDATE 115200
+#define UART_BAUDRATE 115200
#if CONSOLE_IS(pl011_1)
#define UART_BASE VERSAL_NET_UART1_BASE