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| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2023-10-24 16:57:13 +0200 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-10-24 16:57:13 +0200 |
| commit | d6b458e82a06d92a50b6a2abad7a835aabfa2686 (patch) | |
| tree | d650fe56ca44c92d13ca533ca50cf4ac2f13d379 /plat | |
| parent | 3018854b5f229939544ad09c93199ec7b66df358 (diff) | |
| parent | 138ddcbf4d330d13a11576d973513014055f98c1 (diff) | |
Merge changes Ia66dd232,Ie0ddbe0b,Idd191614 into integration
* changes:
fix(rcar3-drivers): update DDR setting
fix(rcar3): fix CPG register code comment
fix(rcar3): update Draak and Eagle board IDs
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/renesas/common/include/registers/cpg_registers.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/renesas/common/include/registers/cpg_registers.h b/plat/renesas/common/include/registers/cpg_registers.h index 5d2bb9e3a..277f11b77 100644 --- a/plat/renesas/common/include/registers/cpg_registers.h +++ b/plat/renesas/common/include/registers/cpg_registers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,7 @@ #define CPG_SRCR2 (CPG_BASE + 0x00B0U) /* CPG module stop status 2 */ #define CPG_MSTPSR2 (CPG_BASE + 0x0040U) -/* CPG module stop status 2 */ +/* CPG module stop status 3 */ #define CPG_MSTPSR3 (CPG_BASE + 0x0048U) /* CPG write protect */ #define CPG_CPGWPR (CPG_BASE + 0x0900U) |