diff options
| author | Karl Li <karl.li@mediatek.corp-partner.google.com> | 2023-08-24 14:14:45 +0800 |
|---|---|---|
| committer | Karl Li <karl.li@mediatek.com> | 2023-10-03 13:27:18 +0800 |
| commit | b254b9815ee25c90264a2305940bc575910f55e4 (patch) | |
| tree | a03917079a8db018beca519cec4d41b6d6245711 /plat | |
| parent | a1377a89a7838669359be3ba351a791405050ccc (diff) | |
feat(mt8188): add DSB before udelay
To ensure that all explicit memory accesses are complete before udelay,
insert dsb before udelay.
Change-Id: If119e920e29539ae8b68d3c44c8f77b5bf424a1a
Signed-off-by: Karl Li <karl.li@mediatek.com>
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c | 1 | ||||
| -rw-r--r-- | plat/mediatek/drivers/apusys/mt8188/apusys_power.c | 12 |
2 files changed, 12 insertions, 1 deletions
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c index c1b3de052..86c4b81c3 100644 --- a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c +++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c @@ -88,6 +88,7 @@ int apusys_kernel_apusys_rv_reset_mp(void) mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST); + dsb(); udelay(RESET_DEALY_US); mmio_write_32(MD32_SYS_CTRL, MD32_G2B_CG_EN | MD32_DBG_EN | MD32_DM_AWUSER_IOMMU_EN | diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c index cdfc13346..0a2781bfc 100644 --- a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c +++ b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c @@ -37,7 +37,6 @@ static int apu_poll(uintptr_t reg, uint32_t mask, uint32_t value, uint32_t timeo if ((reg_val & mask) == value) { return 0; } - udelay(APU_POLL_STEP_US); } while (--count); @@ -169,15 +168,19 @@ int apusys_kernel_apusys_pwr_top_on(void) static void apu_sleep_rpc_rcx(void) { mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_CLR); + dsb(); udelay(10); mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, (RPC_CTRL | RSV10)); + dsb(); udelay(10); mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, CLR_IRQ); + dsb(); udelay(10); mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, SLEEP_REQ); + dsb(); udelay(100); } @@ -313,12 +316,15 @@ static void apu_acc_init(void) static void apu_buck_off_cfg(void) { mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_SET); + dsb(); udelay(10); mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_SET); + dsb(); udelay(10); mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_CLR); + dsb(); udelay(10); } @@ -425,15 +431,19 @@ static void apu_aoc_init(void) { mmio_clrbits_32(SPM_BASE + APUSYS_BUCK_ISOLATION, IPU_EXT_BUCK_ISO); mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_CLR); + dsb(); udelay(10); mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_SET); + dsb(); udelay(10); mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_CLR); + dsb(); udelay(10); mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, SRAM_AOC_ISO_CLR); + dsb(); udelay(10); } |