fix(plat/arm): do not program DSU CLUSTERPWRDN register

This reverts commit 9cf7f355ce8984a4cde970d5f57c913d5247ca6d.

Above mentioned commit was writing to cluster power required bit of
CLUSTERPWRDN register, which provides an advisory status to the power
controller.
Bit definition indication:
0 : Cluster power is not required when all cores are powered down
1 : Cluster power is required even when all cores are powered down
RESET value of this bit is 0

The current implementation in TF-A just programs this bit to 0 when
cluster power down is done but it never sets it to 1. Which actully
does not change any behaviour as the value of this bit always remains 0.

Ideally this bit has to be set to 1 when a core powers up (as RESET
value is 0) and set it to 0 for any core power down except if its last
man standing, in that case we need to ensure the target power level
from OS is cluster then we can do set it to 0.
There also are some investigation needs to be done to find that whether
we need a explicit message to power controller for turning cluster OFF
or it will happen automatically.

Considering this needs a bit of analysis as well as a platform to test
it on, revert the changes which impact the programming during cluster
power down and just keep register defnition.

Change-Id: I4c4ebedae7ca9cd081fb1e0605b9d906d77614d9
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

2 files changed, 1 insertions, 40 deletions

diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index 534a175fc..51dda9ec0 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -65,25 +65,6 @@ static void fvp_cluster_pwrdwn_common(void)
 	/* Disable coherency if this cluster is to be turned off */
 	fvp_interconnect_disable();
 
-#if HW_ASSISTED_COHERENCY
-	uint32_t reg;
-
-	/*
-	 * If we have determined this core to be the last man standing and we
-	 * intend to power down the cluster proactively, we provide a hint to
-	 * the power controller that cluster power is not required when all
-	 * cores are powered down.
-	 * Note that this is only an advisory to power controller and is supported
-	 * by SoCs with DynamIQ Shared Units only.
-	 */
-	reg = read_clusterpwrdn();
-
-	/* Clear and set bit 0 : Cluster power not required */
-	reg &= ~DSU_CLUSTER_PWR_MASK;
-	reg |= DSU_CLUSTER_PWR_OFF;
-	write_clusterpwrdn(reg);
-#endif
-
 	/* Program the power controller to turn the cluster off */
 	fvp_pwrc_write_pcoffr(mpidr);
 }
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index 3222226f7..bb64e734c 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -131,28 +131,8 @@ static void css_power_down_common(const psci_power_state_t *target_state)
 	plat_arm_gic_cpuif_disable();
 
 	/* Cluster is to be turned off, so disable coherency */
-	if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
+	if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
 		plat_arm_interconnect_exit_coherency();
-
-#if HW_ASSISTED_COHERENCY
-		uint32_t reg;
-
-		/*
-		 * If we have determined this core to be the last man standing and we
-		 * intend to power down the cluster proactively, we provide a hint to
-		 * the power controller that cluster power is not required when all
-		 * cores are powered down.
-		 * Note that this is only an advisory to power controller and is supported
-		 * by SoCs with DynamIQ Shared Units only.
-		 */
-		reg = read_clusterpwrdn();
-
-		/* Clear and set bit 0 : Cluster power not required */
-		reg &= ~DSU_CLUSTER_PWR_MASK;
-		reg |= DSU_CLUSTER_PWR_OFF;
-		write_clusterpwrdn(reg);
-#endif
-	}
 }
 
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