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| author | Lauren Wehrmeister <lauren.wehrmeister@arm.com> | 2023-09-22 20:22:19 +0200 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-09-22 20:22:19 +0200 |
| commit | fcfa15d41c8f3adc384f5e21b77e7b2ec6fa76dc (patch) | |
| tree | f44a66719e7929cc547b689b4853bdf7de5080e9 /lib | |
| parent | 1438a5e729e894eb9358732f20641800d956fc6a (diff) | |
| parent | 58dd153cc88e832a6b019f1d4c2e6d64986ea69d (diff) | |
Merge changes from topic "errata" into integration
* changes:
fix(cpus): workaround for Neoverse V2 erratum 2743011
fix(cpus): workaround for Neoverse V2 erratum 2779510
fix(cpus): workaround for Neoverse V2 erratum 2719105
fix(cpus): workaround for Neoverse V2 erratum 2331132
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/neoverse_v2.S | 26 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 16 |
2 files changed, 42 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S index 36ae4deb7..bfd088d50 100644 --- a/lib/cpus/aarch64/neoverse_v2.S +++ b/lib/cpus/aarch64/neoverse_v2.S @@ -22,6 +22,32 @@ #error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132 + sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ + NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH +workaround_reset_end neoverse_v2, ERRATUM(2331132) + +check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) + +workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 + sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 +workaround_reset_end neoverse_v2, ERRATUM(2719105) + +check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) + +workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 + sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 + sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 +workaround_reset_end neoverse_v2, ERRATUM(2743011) + +check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) + +workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 + sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 +workaround_reset_end neoverse_v2, ERRATUM(2779510) + +check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) + workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 /* dsb before isb of power down sequence */ dsb sy diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 0d8f4d4e0..77cc41e03 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -794,10 +794,26 @@ CPU_FLAG_LIST += ERRATA_A510_2666669 # Cortex-A510 cpu and is fixed in r1p3. CPU_FLAG_LIST += ERRATA_A510_2684597 +# Flag to apply erratum 2331132 workaround during reset. This erratum applies +# to revisions r0p0, r0p1 and r0p2. It is still open. +CPU_FLAG_LIST += ERRATA_V2_2331132 + # Flag to apply erratum 2719103 workaround for non-arm interconnect ip. This # erratum applies to revisions r0p0, rop1. Fixed in r0p2. CPU_FLAG_LIST += ERRATA_V2_2719103 +# Flag to apply erratum 2719105 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1. It is fixed in r0p2. +CPU_FLAG_LIST += ERRATA_V2_2719105 + +# Flag to apply erratum 2743011 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1. It is fixed in r0p2. +CPU_FLAG_LIST += ERRATA_V2_2743011 + +# Flag to apply erratum 2779510 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1. It is fixed in r0p2. +CPU_FLAG_LIST += ERRATA_V2_2779510 + # Flag to apply erratum 2801372 workaround for all configurations. # This erratum applies to revisions r0p0, r0p1. Fixed in r0p2. CPU_FLAG_LIST += ERRATA_V2_2801372 |