diff options
| author | Arvind Ram Prakash <arvind.ramprakash@arm.com> | 2023-07-21 16:01:22 -0500 |
|---|---|---|
| committer | Arvind Ram Prakash <arvind.ramprakash@arm.com> | 2023-08-03 23:02:39 +0200 |
| commit | f6af21852d5837e2b0f69dc513e362e9d2f26477 (patch) | |
| tree | 9f52fb44cb88ae01e9a97e6540d05cc6c0d88b96 /lib | |
| parent | 7f798aaa3ea7bed86876fbbc18ce0097814964ff (diff) | |
refactor(cpus): convert Neoverse V1 to use CPU helpers
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idb4b47982278cda93a7c0f0a49dfceb75b8d88e4
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/neoverse_v1.S | 49 |
1 files changed, 13 insertions, 36 deletions
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index d78a242cd..35d2c480f 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -83,36 +83,28 @@ check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0) workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420 /* Set bit 53 in CPUECTLR_EL1 */ - mrs x1, NEOVERSE_V1_CPUECTLR_EL1 - orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53 - msr NEOVERSE_V1_CPUECTLR_EL1, x1 + sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53 workaround_reset_end neoverse_v1, ERRATUM(1774420) check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0) workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573 /* Set bit 2 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_V1_ACTLR2_EL1 - orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 - msr NEOVERSE_V1_ACTLR2_EL1, x1 + sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2 workaround_reset_end neoverse_v1, ERRATUM(1791573) check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0) workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267 /* Set bit 28 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_V1_ACTLR2_EL1 - orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28 - msr NEOVERSE_V1_ACTLR2_EL1, x1 + sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28 workaround_reset_end neoverse_v1, ERRATUM(1852267) check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0) workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756 /* Set bit 8 in CPUECTLR_EL1 */ - mrs x1, NEOVERSE_V1_CPUECTLR_EL1 - orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8 - msr NEOVERSE_V1_CPUECTLR_EL1, x1 + sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8 workaround_reset_end neoverse_v1, ERRATUM(1925756) check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1) @@ -199,18 +191,14 @@ check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1) workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912 /* Set bit 0 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_V1_ACTLR2_EL1 - orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_0 - msr NEOVERSE_V1_ACTLR2_EL1, x1 + sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0 workaround_reset_end neoverse_v1, ERRATUM(2294912) check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 1) workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203 /* Set bit 40 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_V1_ACTLR2_EL1 - orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_40 - msr NEOVERSE_V1_ACTLR2_EL1, x1 + sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40 workaround_reset_end neoverse_v1, ERRATUM(2372203) check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1) @@ -223,18 +211,14 @@ workaround_runtime_end neoverse_v1, ERRATUM(2743093) check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2) workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233 - mrs x1, NEOVERSE_V1_ACTLR5_EL1 - bic x1, x1, #BIT(56) - orr x1, x1, #BIT(55) - msr NEOVERSE_V1_ACTLR5_EL1, x1 + sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56 + sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55 workaround_reset_end neoverse_v1, ERRATUM(2743233) check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2) workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461 - mrs x1, NEOVERSE_V1_ACTLR3_EL1 - orr x1, x1, #BIT(47) - msr NEOVERSE_V1_ACTLR3_EL1, x1 + sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47 workaround_reset_end neoverse_v1, ERRATUM(2779461) check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2) @@ -246,8 +230,7 @@ workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960 * The Neoverse-V1 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. */ - adr x0, wa_cve_vbar_neoverse_v1 - msr vbar_el3, x0 + override_vector_table wa_cve_vbar_neoverse_v1 #endif /* IMAGE_BL31 */ workaround_reset_end neoverse_v1, CVE(2022,23960) @@ -262,15 +245,9 @@ func neoverse_v1_core_pwr_dwn * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 - orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 -#if ERRATA_V1_2743093 - mov x15, x30 - bl cpu_get_rev_var - bl erratum_neoverse_v1_2743093_wa - mov x30, x15 -#endif /* ERRATA_V1_2743093 */ + sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093 + isb ret endfunc neoverse_v1_core_pwr_dwn |