diff options
| author | Manish Pandey <manish.pandey2@arm.com> | 2023-08-30 16:19:26 +0200 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-08-30 16:19:26 +0200 |
| commit | 6a62ddff783a642bb420ba3545678e473af715d5 (patch) | |
| tree | c5da297ee302677ae07f782f10d25766e181fa0c /lib | |
| parent | 34e7cf75510ffeca513cebf08bb2cf26f347406b (diff) | |
| parent | 4a530b4c6556c87deb22c027dfaf2c5d6c9997a3 (diff) | |
Merge "feat(cpufeat): initialize HFG*_EL2 registers" into integration
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 0ac2d6e0c..b16c1139c 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -279,6 +279,20 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info * write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, HCRX_EL2_INIT_VAL); } + + if (is_feat_fgt_supported()) { + /* + * Initialize HFG*_EL2 registers with a default value so legacy + * systems unaware of FEAT_FGT do not get trapped due to their lack + * of initialization for this feature. + */ + write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2, + HFGITR_EL2_INIT_VAL); + write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2, + HFGRTR_EL2_INIT_VAL); + write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2, + HFGWTR_EL2_INIT_VAL); + } #endif /* CTX_INCLUDE_EL2_REGS */ manage_extensions_nonsecure(ctx); @@ -829,8 +843,27 @@ void cm_prepare_el3_exit(uint32_t security_state) if (is_feat_hcx_supported()) { write_hcrx_el2(HCRX_EL2_INIT_VAL); } + + /* + * Initialize Fine-grained trap registers introduced + * by FEAT_FGT so all traps are initially disabled when + * switching to EL2 or a lower EL, preventing undesired + * behavior. + */ + if (is_feat_fgt_supported()) { + /* + * Initialize HFG*_EL2 registers with a default + * value so legacy systems unaware of FEAT_FGT + * do not get trapped due to their lack of + * initialization for this feature. + */ + write_hfgitr_el2(HFGITR_EL2_INIT_VAL); + write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); + write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); + } } + if ((scr_el3 & SCR_HCE_BIT) != 0U) { /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), |