diff options
| author | Maksims Svecovs <maksims.svecovs@arm.com> | 2023-02-02 16:10:22 +0000 |
|---|---|---|
| committer | Maksims Svecovs <maksims.svecovs@arm.com> | 2023-02-09 11:46:03 +0000 |
| commit | 01cf14dd41cae9c68cb5e76a815747a0d2a19a4a (patch) | |
| tree | cbe83d567c7a2744c59e8dd2299dd2dfe30d5169 /lib/el3_runtime | |
| parent | 35f81474fb5982046ed57ae8fe8cbad7463cb55c (diff) | |
fix(context-mgmt): enable SCXTNUM access
Enable SCXTNUM_ELx access for lower ELs in non-secure state.
Make realm context setup take this build flag into account but enable it
by default when RME is used.
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: Ieb0186b2fdffad464bb9316fc3973772c9c28cd0
Diffstat (limited to 'lib/el3_runtime')
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 3bcefdb5d..dab25d681 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -169,7 +169,12 @@ static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_inf state = get_el3state_ctx(ctx); scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); - scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; + scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; + +#if ENABLE_FEAT_CSV2_2 + /* Enable access to the SCXTNUM_ELx registers. */ + scr_el3 |= SCR_EnSCXT_BIT; +#endif write_ctx_reg(state, CTX_SCR_EL3, scr_el3); } @@ -222,6 +227,11 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info * scr_el3 |= SCR_TERR_BIT; #endif +#if ENABLE_FEAT_CSV2_2 + /* Enable access to the SCXTNUM_ELx registers. */ + scr_el3 |= SCR_EnSCXT_BIT; +#endif + #ifdef IMAGE_BL31 /* * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as |