diff options
author | Bipin Ravi <bipin.ravi@arm.com> | 2023-08-28 15:56:44 +0200 |
---|---|---|
committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-08-28 15:56:44 +0200 |
commit | fde15ecf035608b267ac3f03d7cfebb3672e297a (patch) | |
tree | 8c3be6503f3bf8b827c190017b9c1651d74f6ec7 /lib/cpus/aarch64 | |
parent | 74e3f593be647d6299de00f0e452dc6d0071f9ff (diff) | |
parent | dbab05efcc33f1da176e10df611a47edc9174612 (diff) |
Merge changes from topic "sm_bk/errata_refactor" into integration
* changes:
refactor(cpus): convert the Cortex-A57 to use cpu helpers
refactor(cpus): convert the Cortex-A57 to use the errata framework
refactor(cpus): reorder Cortex-A57 errata by ascending order
refactor(cpus): add Cortex-A57 errata framework information
refactor(cpus): convert the Cortex-A53 to use cpu helpers
refactor(cpus): convert the Cortex-A53 to use the errata framework
refactor(cpus): reorder Cortex-A53 errata by ascending order
Diffstat (limited to 'lib/cpus/aarch64')
-rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 305 | ||||
-rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 566 |
2 files changed, 161 insertions, 710 deletions
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index ecaf42288..e6fb08a4e 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,19 +12,12 @@ #include <plat_macros.S> #include <lib/cpus/errata.h> -#if A53_DISABLE_NON_TEMPORAL_HINT -#undef ERRATA_A53_836870 -#define ERRATA_A53_836870 1 -#endif - /* --------------------------------------------- * Disable L1 data cache and unified L2 cache * --------------------------------------------- */ func cortex_a53_disable_dcache - mrs x1, sctlr_el3 - bic x1, x1, #SCTLR_C_BIT - msr sctlr_el3, x1 + sysreg_bit_clear sctlr_el3, SCTLR_C_BIT isb ret endfunc cortex_a53_disable_dcache @@ -34,169 +27,38 @@ endfunc cortex_a53_disable_dcache * --------------------------------------------- */ func cortex_a53_disable_smp - mrs x0, CORTEX_A53_ECTLR_EL1 - bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT - msr CORTEX_A53_ECTLR_EL1, x0 + sysreg_bit_clear CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT isb dsb sy ret endfunc cortex_a53_disable_smp - /* --------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #819472. - * This applies only to revision <= r0p1 of Cortex A53. - * Due to the nature of the errata it is applied unconditionally - * when built in, report it as applicable in this case - * --------------------------------------------------- - */ -func check_errata_819472 -#if ERRATA_A53_819472 - mov x0, #ERRATA_APPLIES - ret -#else - mov x1, #0x01 - b cpu_rev_var_ls -#endif -endfunc check_errata_819472 - - /* --------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #824069. - * This applies only to revision <= r0p2 of Cortex A53. - * Due to the nature of the errata it is applied unconditionally - * when built in, report it as applicable in this case - * --------------------------------------------------- - */ -func check_errata_824069 -#if ERRATA_A53_824069 - mov x0, #ERRATA_APPLIES - ret -#else - mov x1, #0x02 - b cpu_rev_var_ls -#endif -endfunc check_errata_824069 - - /* -------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #826319. - * This applies only to revision <= r0p2 of Cortex A53. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a53_826319_wa - /* - * Compare x0 against revision r0p2 - */ - mov x17, x30 - bl check_errata_826319 - cbz x0, 1f +/* Due to the nature of the errata it is applied unconditionally when chosen */ +check_erratum_ls cortex_a53, ERRATUM(819472), CPU_REV(0, 1) +/* erratum workaround is interleaved with generic code */ +add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET + +/* Due to the nature of the errata it is applied unconditionally when chosen */ +check_erratum_ls cortex_a53, ERRATUM(824069), CPU_REV(0, 2) +/* erratum workaround is interleaved with generic code */ +add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET + +workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319 mrs x1, CORTEX_A53_L2ACTLR_EL1 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH msr CORTEX_A53_L2ACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a53_826319_wa - -func check_errata_826319 - mov x1, #0x02 - b cpu_rev_var_ls -endfunc check_errata_826319 - - /* --------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #827319. - * This applies only to revision <= r0p2 of Cortex A53. - * Due to the nature of the errata it is applied unconditionally - * when built in, report it as applicable in this case - * --------------------------------------------------- - */ -func check_errata_827319 -#if ERRATA_A53_827319 - mov x0, #ERRATA_APPLIES - ret -#else - mov x1, #0x02 - b cpu_rev_var_ls -#endif -endfunc check_errata_827319 +workaround_reset_end cortex_a53, ERRATUM(826319) - /* --------------------------------------------------------------------- - * Disable the cache non-temporal hint. - * - * This ignores the Transient allocation hint in the MAIR and treats - * allocations the same as non-transient allocation types. As a result, - * the LDNP and STNP instructions in AArch64 behave the same as the - * equivalent LDP and STP instructions. - * - * This is relevant only for revisions <= r0p3 of Cortex-A53. - * From r0p4 and onwards, the bit to disable the hint is enabled by - * default at reset. - * - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------------- - */ -func a53_disable_non_temporal_hint - /* - * Compare x0 against revision r0p3 - */ - mov x17, x30 - bl check_errata_disable_non_temporal_hint - cbz x0, 1f - mrs x1, CORTEX_A53_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH - msr CORTEX_A53_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc a53_disable_non_temporal_hint - -func check_errata_disable_non_temporal_hint - mov x1, #0x03 - b cpu_rev_var_ls -endfunc check_errata_disable_non_temporal_hint - - /* -------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #855873. - * - * This applies only to revisions >= r0p3 of Cortex A53. - * Earlier revisions of the core are affected as well, but don't - * have the chicken bit in the CPUACTLR register. It is expected that - * the rich OS takes care of that, especially as the workaround is - * shared with other erratas in those revisions of the CPU. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a53_855873_wa - /* - * Compare x0 against revision r0p3 and higher - */ - mov x17, x30 - bl check_errata_855873 - cbz x0, 1f - - mrs x1, CORTEX_A53_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI - msr CORTEX_A53_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a53_855873_wa - -func check_errata_855873 - mov x1, #0x03 - b cpu_rev_var_hs -endfunc check_errata_855873 +check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2) -/* - * Errata workaround for Cortex A53 Errata #835769. - * This applies to revisions <= r0p4 of Cortex A53. - * This workaround is statically enabled at build time. - */ -func check_errata_835769 - cmp x0, #0x04 +/* Due to the nature of the errata it is applied unconditionally when chosen */ +check_erratum_ls cortex_a53, ERRATUM(827319), CPU_REV(0, 2) +/* erratum workaround is interleaved with generic code */ +add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET + +check_erratum_custom_start cortex_a53, ERRATUM(835769) + cmp x0, CPU_REV(0, 4) b.hi errata_not_applies /* * Fix potentially available for revisions r0p2, r0p3 and r0p4. @@ -213,17 +75,29 @@ errata_not_applies: mov x0, #ERRATA_NOT_APPLIES exit_check_errata_835769: ret -endfunc check_errata_835769 +check_erratum_custom_end cortex_a53, ERRATUM(835769) -/* - * Errata workaround for Cortex A53 Errata #843419. - * This applies to revisions <= r0p4 of Cortex A53. - * This workaround is statically enabled at build time. - */ -func check_errata_843419 +/* workaround at build time */ +add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769, NO_APPLY_AT_RESET + + /* + * Disable the cache non-temporal hint. + * + * This ignores the Transient allocation hint in the MAIR and treats + * allocations the same as non-transient allocation types. As a result, + * the LDNP and STNP instructions in AArch64 behave the same as the + * equivalent LDP and STP instructions. + */ +workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT + sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_DTAH +workaround_reset_end cortex_a53, ERRATUM(836870) + +check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3) + +check_erratum_custom_start cortex_a53, ERRATUM(843419) mov x1, #ERRATA_APPLIES mov x2, #ERRATA_NOT_APPLIES - cmp x0, #0x04 + cmp x0, CPU_REV(0, 4) csel x0, x1, x2, ls /* * Fix potentially available for revision r0p4. @@ -237,58 +111,32 @@ func check_errata_843419 mov x0, x2 exit_check_errata_843419: ret -endfunc check_errata_843419 +check_erratum_custom_end cortex_a53, ERRATUM(843419) - /* -------------------------------------------------- - * Errata workaround for Cortex A53 Errata #1530924. - * This applies to all revisions of Cortex A53. - * -------------------------------------------------- - */ -func check_errata_1530924 -#if ERRATA_A53_1530924 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_1530924 +/* workaround at build time */ +add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419, NO_APPLY_AT_RESET - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A53. - * Shall clobber: x0-x19 - * ------------------------------------------------- + /* + * Earlier revisions of the core are affected as well, but don't + * have the chicken bit in the CPUACTLR register. It is expected that + * the rich OS takes care of that, especially as the workaround is + * shared with other erratas in those revisions of the CPU. */ -func cortex_a53_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 +workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873 + sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_ENDCCASCI +workaround_reset_end cortex_a53, ERRATUM(855873) +check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3) -#if ERRATA_A53_826319 - mov x0, x18 - bl errata_a53_826319_wa -#endif +check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924 -#if ERRATA_A53_836870 - mov x0, x18 - bl a53_disable_non_temporal_hint -#endif +/* erratum has no workaround in the cpu. Generic code must take care */ +add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924, NO_APPLY_AT_RESET -#if ERRATA_A53_855873 - mov x0, x18 - bl errata_a53_855873_wa -#endif - - /* --------------------------------------------- - * Enable the SMP bit. - * --------------------------------------------- - */ - mrs x0, CORTEX_A53_ECTLR_EL1 - orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT - msr CORTEX_A53_ECTLR_EL1, x0 - isb - ret x19 -endfunc cortex_a53_reset_func +cpu_reset_func_start cortex_a53 + /* Enable the SMP bit. */ + sysreg_bit_set CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT +cpu_reset_func_end cortex_a53 func cortex_a53_core_pwr_dwn mov x18, x30 @@ -351,34 +199,7 @@ func cortex_a53_cluster_pwr_dwn b cortex_a53_disable_smp endfunc cortex_a53_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A53. Must follow AAPCS. - */ -func cortex_a53_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A53_819472, cortex_a53, 819472 - report_errata ERRATA_A53_824069, cortex_a53, 824069 - report_errata ERRATA_A53_826319, cortex_a53, 826319 - report_errata ERRATA_A53_827319, cortex_a53, 827319 - report_errata ERRATA_A53_835769, cortex_a53, 835769 - report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint - report_errata ERRATA_A53_843419, cortex_a53, 843419 - report_errata ERRATA_A53_855873, cortex_a53, 855873 - report_errata ERRATA_A53_1530924, cortex_a53, 1530924 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a53_errata_report -#endif +errata_report_shim cortex_a53 /* --------------------------------------------- * This function provides cortex_a53 specific diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 3766ec769..8fafacab4 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -18,9 +18,7 @@ * --------------------------------------------- */ func cortex_a57_disable_dcache - mrs x1, sctlr_el3 - bic x1, x1, #SCTLR_C_BIT - msr sctlr_el3, x1 + sysreg_bit_clear sctlr_el3, SCTLR_C_BIT isb ret endfunc cortex_a57_disable_dcache @@ -46,9 +44,7 @@ endfunc cortex_a57_disable_l2_prefetch * --------------------------------------------- */ func cortex_a57_disable_smp - mrs x0, CORTEX_A57_ECTLR_EL1 - bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT - msr CORTEX_A57_ECTLR_EL1, x0 + sysreg_bit_clear CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT ret endfunc cortex_a57_disable_smp @@ -60,227 +56,66 @@ func cortex_a57_disable_ext_debug mov x0, #1 msr osdlr_el1, x0 isb -#if ERRATA_A57_817169 - /* - * Invalidate any TLB address - */ - mov x0, #0 - tlbi vae3, x0 -#endif + + apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169 + dsb sy ret endfunc cortex_a57_disable_ext_debug - /* -------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #806969. - * This applies only to revision r0p0 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a57_806969_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_806969 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_806969_wa - -func check_errata_806969 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_806969 - - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #813419. - * This applies only to revision r0p0 of Cortex A57. - * --------------------------------------------------- - */ -func check_errata_813419 - /* - * Even though this is only needed for revision r0p0, it - * is always applied due to limitations of the current - * errata framework. - */ - mov x0, #ERRATA_APPLIES - ret -endfunc check_errata_813419 - - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #813420. - * This applies only to revision r0p0 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_813420_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_813420 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_813420_wa - -func check_errata_813420 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_813420 - - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #814670. - * This applies only to revision r0p0 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_814670_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_814670 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION - msr CORTEX_A57_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a57_814670_wa +/* + * Disable the over-read from the LDNP/STNP instruction. The SDEN doesn't + * provide and erratum number, so assign it an obvious 1 + */ +workaround_reset_start cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD +workaround_reset_end cortex_a57, ERRATUM(1) -func check_errata_814670 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_814670 +check_erratum_ls cortex_a57, ERRATUM(1), CPU_REV(1, 2) - /* ---------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #817169. - * This applies only to revision <= r0p1 of Cortex A57. - * ---------------------------------------------------- - */ -func check_errata_817169 - /* - * Even though this is only needed for revision <= r0p1, it - * is always applied because of the low cost of the workaround. - */ - mov x0, #ERRATA_APPLIES - ret -endfunc check_errata_817169 - - /* -------------------------------------------------------------------- - * Disable the over-read from the LDNP instruction. - * - * This applies to all revisions <= r1p2. The performance degradation - * observed with LDNP/STNP has been fixed on r1p3 and onwards. - * - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------------- - */ -func a57_disable_ldnp_overread - /* - * Compare x0 against revision r1p2 - */ - mov x17, x30 - bl check_errata_disable_ldnp_overread - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc a57_disable_ldnp_overread - -func check_errata_disable_ldnp_overread - mov x1, #0x12 - b cpu_rev_var_ls -endfunc check_errata_disable_ldnp_overread - - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #826974. - * This applies only to revision <= r1p1 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_826974_wa - /* - * Compare x0 against revision r1p1 - */ - mov x17, x30 - bl check_errata_826974 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_826974_wa - -func check_errata_826974 - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_826974 - - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #826977. - * This applies only to revision <= r1p1 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_826977_wa - /* - * Compare x0 against revision r1p1 - */ - mov x17, x30 - bl check_errata_826977 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_826977_wa - -func check_errata_826977 - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_826977 - - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #828024. - * This applies only to revision <= r1p1 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_828024_wa - /* - * Compare x0 against revision r1p1 - */ - mov x17, x30 - bl check_errata_828024 - cbz x0, 1f +workaround_reset_start cortex_a57, ERRATUM(806969), ERRATA_A57_806969 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA +workaround_reset_end cortex_a57, ERRATUM(806969) + +check_erratum_ls cortex_a57, ERRATUM(806969), CPU_REV(0, 0) + +/* erratum always worked around, but report it correctly */ +check_erratum_ls cortex_a57, ERRATUM(813419), CPU_REV(0, 0) +add_erratum_entry cortex_a57, ERRATUM(813419), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET + +workaround_reset_start cortex_a57, ERRATUM(813420), ERRATA_A57_813420 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI +workaround_reset_end cortex_a57, ERRATUM(813420) + +check_erratum_ls cortex_a57, ERRATUM(813420), CPU_REV(0, 0) + +workaround_reset_start cortex_a57, ERRATUM(814670), ERRATA_A57_814670 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION +workaround_reset_end cortex_a57, ERRATUM(814670) + +check_erratum_ls cortex_a57, ERRATUM(814670), CPU_REV(0, 0) + +workaround_runtime_start cortex_a57, ERRATUM(817169), ERRATA_A57_817169, CORTEX_A57_MIDR + /* Invalidate any TLB address */ + mov x0, #0 + tlbi vae3, x0 +workaround_runtime_end cortex_a57, ERRATUM(817169), NO_ISB + +check_erratum_ls cortex_a57, ERRATUM(817169), CPU_REV(0, 1) + +workaround_reset_start cortex_a57, ERRATUM(826974), ERRATA_A57_826974 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB +workaround_reset_end cortex_a57, ERRATUM(826974) + +check_erratum_ls cortex_a57, ERRATUM(826974), CPU_REV(1, 1) + +workaround_reset_start cortex_a57, ERRATUM(826977), ERRATA_A57_826977 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE +workaround_reset_end cortex_a57, ERRATUM(826977) + +check_erratum_ls cortex_a57, ERRATUM(826977), CPU_REV(1, 1) + +workaround_reset_start cortex_a57, ERRATUM(828024), ERRATA_A57_828024 mrs x1, CORTEX_A57_CPUACTLR_EL1 /* * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 @@ -291,234 +126,64 @@ func errata_a57_828024_wa orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \ CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING) msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_828024_wa - -func check_errata_828024 - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_828024 - - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #829520. - * This applies only to revision <= r1p2 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_829520_wa - /* - * Compare x0 against revision r1p2 - */ - mov x17, x30 - bl check_errata_829520 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_829520_wa - -func check_errata_829520 - mov x1, #0x12 - b cpu_rev_var_ls -endfunc check_errata_829520 - - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #833471. - * This applies only to revision <= r1p2 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_833471_wa - /* - * Compare x0 against revision r1p2 - */ - mov x17, x30 - bl check_errata_833471 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_833471_wa - -func check_errata_833471 - mov x1, #0x12 - b cpu_rev_var_ls -endfunc check_errata_833471 - - /* -------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #859972. - * This applies only to revision <= r1p3 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: - * -------------------------------------------------- - */ -func errata_a57_859972_wa - mov x17, x30 - bl check_errata_859972 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_859972_wa +workaround_reset_end cortex_a57, ERRATUM(828024) -func check_errata_859972 - mov x1, #0x13 - b cpu_rev_var_ls -endfunc check_errata_859972 +check_erratum_ls cortex_a57, ERRATUM(828024), CPU_REV(1, 1) -func check_errata_cve_2017_5715 -#if WORKAROUND_CVE_2017_5715 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2017_5715 +workaround_reset_start cortex_a57, ERRATUM(829520), ERRATA_A57_829520 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR +workaround_reset_end cortex_a57, ERRATUM(829520) -func check_errata_cve_2018_3639 -#if WORKAROUND_CVE_2018_3639 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2018_3639 +check_erratum_ls cortex_a57, ERRATUM(829520), CPU_REV(1, 2) - /* -------------------------------------------------- - * Errata workaround for Cortex A57 Errata #1319537. - * This applies to all revisions of Cortex A57. - * -------------------------------------------------- - */ -func check_errata_1319537 -#if ERRATA_A57_1319537 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_1319537 +workaround_reset_start cortex_a57, ERRATUM(833471), ERRATA_A57_833471 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH +workaround_reset_end cortex_a57, ERRATUM(833471) - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A57. - * Shall clobber: x0-x19 - * ------------------------------------------------- - */ -func cortex_a57_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_A57_806969 - mov x0, x18 - bl errata_a57_806969_wa -#endif +check_erratum_ls cortex_a57, ERRATUM(833471), CPU_REV(1, 2) -#if ERRATA_A57_813420 - mov x0, x18 - bl errata_a57_813420_wa -#endif +workaround_reset_start cortex_a57, ERRATUM(859972), ERRATA_A57_859972 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH +workaround_reset_end cortex_a57, ERRATUM(859972) -#if ERRATA_A57_814670 - mov x0, x18 - bl errata_a57_814670_wa -#endif +check_erratum_ls cortex_a57, ERRATUM(859972), CPU_REV(1, 3) -#if A57_DISABLE_NON_TEMPORAL_HINT - mov x0, x18 - bl a57_disable_ldnp_overread -#endif +check_erratum_chosen cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537 +/* erratum has no workaround in the cpu. Generic code must take care */ +add_erratum_entry cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537, NO_APPLY_AT_RESET -#if ERRATA_A57_826974 - mov x0, x18 - bl errata_a57_826974_wa +workaround_reset_start cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 +#if IMAGE_BL31 + override_vector_table wa_cve_2017_5715_mmu_vbar #endif +workaround_reset_end cortex_a57, CVE(2017, 5715) -#if ERRATA_A57_826977 - mov x0, x18 - bl errata_a57_826977_wa -#endif +check_erratum_chosen cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 -#if ERRATA_A57_828024 - mov x0, x18 - bl errata_a57_828024_wa -#endif - -#if ERRATA_A57_829520 - mov x0, x18 - bl errata_a57_829520_wa -#endif - -#if ERRATA_A57_833471 - mov x0, x18 - bl errata_a57_833471_wa -#endif - -#if ERRATA_A57_859972 - mov x0, x18 - bl errata_a57_859972_wa -#endif - -#if IMAGE_BL31 && ( WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 ) - /* --------------------------------------------------------------- - * Override vector table & enable existing workaround if either of - * the build flags are enabled - * --------------------------------------------------------------- - */ - adr x0, wa_cve_2017_5715_mmu_vbar - msr vbar_el3, x0 - /* isb will be performed before returning from this function */ -#endif - -#if WORKAROUND_CVE_2018_3639 - mrs x0, CORTEX_A57_CPUACTLR_EL1 - orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE - msr CORTEX_A57_CPUACTLR_EL1, x0 +workaround_reset_start cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE isb dsb sy -#endif +workaround_reset_end cortex_a57, CVE(2018, 3639) -#if A57_ENABLE_NONCACHEABLE_LOAD_FWD - /* --------------------------------------------- - * Enable higher performance non-cacheable load - * forwarding - * --------------------------------------------- - */ - mrs x0, CORTEX_A57_CPUACTLR_EL1 - orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD - msr CORTEX_A57_CPUACTLR_EL1, x0 +check_erratum_chosen cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + +workaround_reset_start cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + override_vector_table wa_cve_2017_5715_mmu_vbar #endif +workaround_reset_end cortex_a57, CVE(2022, 23960) - /* --------------------------------------------- - * Enable the SMP bit. - * --------------------------------------------- - */ - mrs x0, CORTEX_A57_ECTLR_EL1 - orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT - msr CORTEX_A57_ECTLR_EL1, x0 - isb - ret x19 -endfunc cortex_a57_reset_func +check_erratum_chosen cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING +cpu_reset_func_start cortex_a57 +#if A57_ENABLE_NONCACHEABLE_LOAD_FWD + /* Enable higher performance non-cacheable load forwarding */ + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD #endif - ret -endfunc check_errata_cve_2022_23960 + /* Enable the SMP bit. */ + sysreg_bit_set CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT +cpu_reset_func_end cortex_a57 func check_smccc_arch_workaround_3 mov x0, #ERRATA_APPLIES @@ -619,42 +284,7 @@ func cortex_a57_cluster_pwr_dwn b cortex_a57_disable_ext_debug endfunc cortex_a57_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A57. Must follow AAPCS. - */ -func cortex_a57_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A57_806969, cortex_a57, 806969 - report_errata ERRATA_A57_813419, cortex_a57, 813419 - report_errata ERRATA_A57_813420, cortex_a57, 813420 - report_errata ERRATA_A57_814670, cortex_a57, 814670 - report_errata ERRATA_A57_817169, cortex_a57, 817169 - report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ - disable_ldnp_overread - report_errata ERRATA_A57_826974, cortex_a57, 826974 - report_errata ERRATA_A57_826977, cortex_a57, 826977 - report_errata ERRATA_A57_828024, cortex_a57, 828024 - report_errata ERRATA_A57_829520, cortex_a57, 829520 - report_errata ERRATA_A57_833471, cortex_a57, 833471 - report_errata ERRATA_A57_859972, cortex_a57, 859972 - report_errata ERRATA_A57_1319537, cortex_a57, 1319537 - report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 - report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639 - report_errata WORKAROUND_CVE_2022_23960, cortex_a57, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a57_errata_report -#endif +errata_report_shim cortex_a57 /* --------------------------------------------- * This function provides cortex_a57 specific @@ -679,7 +309,7 @@ endfunc cortex_a57_cpu_reg_dump declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \ cortex_a57_reset_func, \ - check_errata_cve_2017_5715, \ + check_erratum_cortex_a57_5715, \ CPU_NO_EXTRA2_FUNC, \ check_smccc_arch_workaround_3, \ cortex_a57_core_pwr_dwn, \ |