diff options
author | Bipin Ravi <bipin.ravi@arm.com> | 2023-10-17 07:55:55 -0500 |
---|---|---|
committer | laurenw-arm <lauren.wehrmeister@arm.com> | 2023-11-02 10:12:36 -0500 |
commit | d7bc2cb4303088873a715bcaa2ac3e0096b9d7f2 (patch) | |
tree | a93e47fc9655b7f6e06a4645eb68a328f4db41f0 /lib/cpus/aarch64 | |
parent | 68085ad4827ac7daa39767d479d0565daa32cb47 (diff) |
fix(cpus): workaround for Cortex-A710 erratum 2742423
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest
Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Diffstat (limited to 'lib/cpus/aarch64')
-rw-r--r-- | lib/cpus/aarch64/cortex_a710.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index c618d986e..f3931d743 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -178,6 +178,14 @@ workaround_reset_end cortex_a710, ERRATUM(2371105) check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) +workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 + /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ + sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) + sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) +workaround_reset_end cortex_a710, ERRATUM(2742423) + +check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) + workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 /* dsb before isb of power down sequence */ dsb sy |