Merge changes from topic "sm/errata_refactor" into integration

* changes:
  refactor(cpus): convert Cortex-A15 to use the errata framework
  refactor(cpus): convert the Cortex-X3 to use the cpu helpers
  refactor(cpus): convert Cortex-X3 to use the errata framework
  refactor(cpus): reorder Cortex-X3 errata by ascending order
  refactor(cpus): convert the Cortex-A73 to use the cpu helpers
  refactor(cpus): convert Cortex-A73 to use the errata framework
  refactor(cpus): reorder Cortex-A73 errata by ascending order
  refactor(cpus): convert the Cortex-A35 to use the cpu helpers
  refactor(cpus): convert Cortex-A35 to use the errata framework

3 files changed, 114 insertions, 359 deletions

diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S
index be3c652cc..6ffb94407 100644
--- a/lib/cpus/aarch64/cortex_a35.S
+++ b/lib/cpus/aarch64/cortex_a35.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,9 +16,7 @@
 	 * ---------------------------------------------
 	 */
 func cortex_a35_disable_dcache
-	mrs	x1, sctlr_el3
-	bic	x1, x1, #SCTLR_C_BIT
-	msr	sctlr_el3, x1
+	sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
 	isb
 	ret
 endfunc cortex_a35_disable_dcache
@@ -28,65 +26,29 @@ endfunc cortex_a35_disable_dcache
 	 * ---------------------------------------------
 	 */
 func cortex_a35_disable_smp
-	mrs	x0, CORTEX_A35_CPUECTLR_EL1
-	bic	x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
-	msr	CORTEX_A35_CPUECTLR_EL1, x0
+	sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
 	isb
 	dsb	sy
 	ret
 endfunc cortex_a35_disable_smp
 
-	 /* ---------------------------------------------------
-	 * Errata Workaround for Cortex A35 Errata #855472.
-	 * This applies to revisions r0p0 of Cortex A35.
-	 * Inputs:
-	 * x0: variant[4:7] and revision[0:3] of current cpu.
-	 * Shall clobber: x0-x17
-	 * ---------------------------------------------------
-	 */
-func errata_a35_855472_wa
-	 /*
-	  * Compare x0 against revision r0p0
-	  */
-	 mov	x17, x30
-	 bl	check_errata_855472
-	 cbz	x0, 1f
-	 mrs	x1, CORTEX_A35_CPUACTLR_EL1
-	 orr	x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
-	 msr	CORTEX_A35_CPUACTLR_EL1, x1
-	 isb
-1:
-	ret	x17
-endfunc errata_a35_855472_wa
-
-func check_errata_855472
-	mov	x1, #0x00
-	b	cpu_rev_var_ls
-endfunc check_errata_855472
+workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472
+	sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
+workaround_reset_end cortex_a35, ERRATUM(855472)
+
+check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0)
 
 	/* -------------------------------------------------
 	 * The CPU Ops reset function for Cortex-A35.
-	 * Clobbers: x0
 	 * -------------------------------------------------
 	 */
-func cortex_a35_reset_func
-	mov	x19, x30
-	bl	cpu_get_rev_var
-
-#if ERRATA_A35_855472
-	bl	errata_a35_855472_wa
-#endif
-
+cpu_reset_func_start cortex_a35
 	/* ---------------------------------------------
 	 * Enable the SMP bit.
 	 * ---------------------------------------------
 	 */
-	mrs	x0, CORTEX_A35_CPUECTLR_EL1
-	orr	x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
-	msr	CORTEX_A35_CPUECTLR_EL1, x0
-	isb
-	ret	x19
-endfunc cortex_a35_reset_func
+	sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
+cpu_reset_func_end cortex_a35
 
 func cortex_a35_core_pwr_dwn
 	mov	x18, x30
@@ -149,27 +111,7 @@ func cortex_a35_cluster_pwr_dwn
 	b	cortex_a35_disable_smp
 endfunc cortex_a35_cluster_pwr_dwn
 
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A35. Must follow AAPCS.
- */
-func cortex_a35_errata_report
-	stp	x8, x30, [sp, #-16]!
-
-	bl	cpu_get_rev_var
-	mov	x8, x0
-
-	/*
-	 * Report all errata. The revision-variant information is passed to
-	 * checking functions of each errata.
-	 */
-	report_errata ERRATA_A35_855472, cortex_a35, 855472
-
-	ldp	x8, x30, [sp], #16
-	ret
-endfunc cortex_a35_errata_report
-#endif
-
+errata_report_shim cortex_a35
 
 	/* ---------------------------------------------
 	 * This function provides cortex_a35 specific
diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index edcd1f51c..a7435c70f 100644
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,9 +15,7 @@
 	 * ---------------------------------------------
 	 */
 func cortex_a73_disable_dcache
-	mrs	x1, sctlr_el3
-	bic	x1, x1, #SCTLR_C_BIT
-	msr	sctlr_el3, x1
+	sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
 	isb
 	ret
 endfunc cortex_a73_disable_dcache
@@ -27,124 +25,95 @@ endfunc cortex_a73_disable_dcache
 	 * ---------------------------------------------
 	 */
 func cortex_a73_disable_smp
-	mrs	x0, CORTEX_A73_CPUECTLR_EL1
-	bic	x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
-	msr	CORTEX_A73_CPUECTLR_EL1, x0
+	sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT
 	isb
 	dsb	sy
 	ret
 endfunc cortex_a73_disable_smp
 
-	/* ---------------------------------------------------
-	 * Errata Workaround for Cortex A73 Errata #852427.
-	 * This applies only to revision r0p0 of Cortex A73.
-	 * Inputs:
-	 * x0: variant[4:7] and revision[0:3] of current cpu.
-	 * Shall clobber: x0-x17
-	 * ---------------------------------------------------
-	 */
-func errata_a73_852427_wa
-	/*
-	 * Compare x0 against revision r0p0
-	 */
-	mov	x17, x30
-	bl	check_errata_852427
-	cbz	x0, 1f
-	mrs	x1, CORTEX_A73_DIAGNOSTIC_REGISTER
-	orr	x1, x1, #(1 << 12)
-	msr	CORTEX_A73_DIAGNOSTIC_REGISTER, x1
-	isb
-1:
-	ret	x17
-endfunc errata_a73_852427_wa
+func check_smccc_arch_workaround_3
+	mov	x0, #ERRATA_APPLIES
+	ret
+endfunc check_smccc_arch_workaround_3
 
-func check_errata_852427
-	mov	x1, #0x00
-	b	cpu_rev_var_ls
-endfunc check_errata_852427
+workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427
+	sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12)
+workaround_reset_end cortex_a73, ERRATUM(852427)
 
-	/* ---------------------------------------------------
-	 * Errata Workaround for Cortex A73 Errata #855423.
-	 * This applies only to revision <= r0p1 of Cortex A73.
-	 * Inputs:
-	 * x0: variant[4:7] and revision[0:3] of current cpu.
-	 * Shall clobber: x0-x17
-	 * ---------------------------------------------------
-	 */
-func errata_a73_855423_wa
-	/*
-	 * Compare x0 against revision r0p1
-	 */
-	mov	x17, x30
-	bl	check_errata_855423
-	cbz	x0, 1f
-	mrs	x1, CORTEX_A73_IMP_DEF_REG2
-	orr	x1, x1, #(1 << 7)
-	msr	CORTEX_A73_IMP_DEF_REG2, x1
-	isb
-1:
-	ret	x17
-endfunc errata_a73_855423_wa
+check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0)
 
-func check_errata_855423
-	mov	x1, #0x01
-	b	cpu_rev_var_ls
-endfunc check_errata_855423
+workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423
+	sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7)
+workaround_reset_end cortex_a73, ERRATUM(855423)
 
-	/* -------------------------------------------------
-	 * The CPU Ops reset function for Cortex-A73.
-	 * -------------------------------------------------
-	 */
+check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1)
 
-func cortex_a73_reset_func
-	mov	x19, x30
-	bl	cpu_get_rev_var
-	mov	x18, x0
+workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+#if IMAGE_BL31
+	override_vector_table wa_cve_2017_5715_bpiall_vbar
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a73, CVE(2017, 5715)
 
-#if ERRATA_A73_852427
-	mov	x0, x18
-	bl	errata_a73_852427_wa
+check_erratum_custom_start cortex_a73, CVE(2017, 5715)
+	cpu_check_csv2	x0, 1f
+#if WORKAROUND_CVE_2017_5715
+	mov	x0, #ERRATA_APPLIES
+#else
+	mov	x0, #ERRATA_MISSING
 #endif
+	ret
+1:
+	mov	x0, #ERRATA_NOT_APPLIES
+	ret
+check_erratum_custom_end cortex_a73, CVE(2017, 5715)
 
-#if ERRATA_A73_855423
-	mov	x0, x18
-	bl	errata_a73_855423_wa
-#endif
+workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+	sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
+workaround_reset_end cortex_a73, CVE(2018, 3639)
 
-#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
-	cpu_check_csv2	x0, 1f
-	adr	x0, wa_cve_2017_5715_bpiall_vbar
-	msr	vbar_el3, x0
-	isb
+check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+
+workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
 	/* Skip installing vector table again for CVE_2022_23960 */
-        b       2f
+	override_vector_table wa_cve_2017_5715_bpiall_vbar
+	cmp	x0, x1
+	b.eq	1f
+	msr     vbar_el3, x0
 1:
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a73, CVE(2022, 23960)
+
+check_erratum_custom_start cortex_a73, CVE(2022, 23960)
+#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
+	cpu_check_csv2  x0, 1f
+	mov	x0, #ERRATA_APPLIES
+	ret
+ 1:
 #if WORKAROUND_CVE_2022_23960
-	adr	x0, wa_cve_2017_5715_bpiall_vbar
-	msr	vbar_el3, x0
-	isb
-#endif
-2:
-#endif /* IMAGE_BL31 &&  (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
+	mov	x0, #ERRATA_APPLIES
+#else
+	mov	x0, #ERRATA_MISSING
+#endif /* WORKAROUND_CVE_2022_23960 */
+	ret
+#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
+	mov	x0, #ERRATA_MISSING
+	ret
+check_erratum_custom_end cortex_a73, CVE(2022, 23960)
 
-#if WORKAROUND_CVE_2018_3639
-	mrs	x0, CORTEX_A73_IMP_DEF_REG1
-	orr	x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
-	msr	CORTEX_A73_IMP_DEF_REG1, x0
-	isb
-#endif
+	/* -------------------------------------------------
+	 * The CPU Ops reset function for Cortex-A73.
+	 * -------------------------------------------------
+	 */
 
+cpu_reset_func_start cortex_a73
 	/* ---------------------------------------------
 	 * Enable the SMP bit.
 	 * Clobbers : x0
 	 * ---------------------------------------------
 	 */
-	mrs	x0, CORTEX_A73_CPUECTLR_EL1
-	orr	x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
-	msr	CORTEX_A73_CPUECTLR_EL1, x0
-	isb
-	ret	x19
-endfunc cortex_a73_reset_func
+	sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT
+cpu_reset_func_end cortex_a73
 
 func cortex_a73_core_pwr_dwn
 	mov	x18, x30
@@ -207,74 +176,8 @@ func cortex_a73_cluster_pwr_dwn
 	b	cortex_a73_disable_smp
 endfunc cortex_a73_cluster_pwr_dwn
 
-func check_errata_cve_2017_5715
-	cpu_check_csv2	x0, 1f
-#if WORKAROUND_CVE_2017_5715
-	mov	x0, #ERRATA_APPLIES
-#else
-	mov	x0, #ERRATA_MISSING
-#endif
-	ret
-1:
-	mov	x0, #ERRATA_NOT_APPLIES
-	ret
-endfunc check_errata_cve_2017_5715
 
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
-	mov	x0, #ERRATA_APPLIES
-#else
-	mov	x0, #ERRATA_MISSING
-#endif
-	ret
-endfunc check_errata_cve_2018_3639
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
-	cpu_check_csv2	x0, 1f
-	mov	x0, #ERRATA_APPLIES
-	ret
- 1:
-# if WORKAROUND_CVE_2022_23960
-	mov	x0, #ERRATA_APPLIES
-# else
-	mov	x0, #ERRATA_MISSING
-# endif /* WORKAROUND_CVE_2022_23960 */
-	ret
-#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
-	mov	x0, #ERRATA_MISSING
-	ret
-endfunc check_errata_cve_2022_23960
-
-func check_smccc_arch_workaround_3
-	mov	x0, #ERRATA_APPLIES
-	ret
-endfunc check_smccc_arch_workaround_3
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A75. Must follow AAPCS.
- */
-func cortex_a73_errata_report
-	stp	x8, x30, [sp, #-16]!
-
-	bl	cpu_get_rev_var
-	mov	x8, x0
-
-	/*
-	 * Report all errata. The revision-variant information is passed to
-	 * checking functions of each errata.
-	 */
-	report_errata ERRATA_A73_852427, cortex_a73, 852427
-	report_errata ERRATA_A73_855423, cortex_a73, 855423
-	report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
-	report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639
-	report_errata WORKAROUND_CVE_2022_23960, cortex_a73, cve_2022_23960
-
-	ldp	x8, x30, [sp], #16
-	ret
-endfunc cortex_a73_errata_report
-#endif
+errata_report_shim cortex_a73
 
 	/* ---------------------------------------------
 	 * This function provides cortex_a73 specific
@@ -298,7 +201,7 @@ endfunc cortex_a73_cpu_reg_dump
 
 declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
 	cortex_a73_reset_func, \
-	check_errata_cve_2017_5715, \
+	check_erratum_cortex_a73_5715, \
 	CPU_NO_EXTRA2_FUNC, \
 	check_smccc_arch_workaround_3, \
 	cortex_a73_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index f104b487f..c781d3832 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,141 +26,51 @@
 	wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
 #endif /* WORKAROUND_CVE_2022_23960 */
 
+workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+	sysreg_bit_set	CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36
+workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB
+
+check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0)
+
+workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812
+	/* Disable retention control for WFI and WFE. */
+	mrs	x0, CORTEX_X3_CPUPWRCTLR_EL1
+	bfi	x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
+	bfi	x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
+	msr	CORTEX_X3_CPUPWRCTLR_EL1, x0
+workaround_reset_end cortex_x3, ERRATUM(2615812)
+
+check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
+
+workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+	override_vector_table wa_cve_vbar_cortex_x3
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x3, CVE(2022, 23960)
+
+check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
+cpu_reset_func_start cortex_x3
+	/* Disable speculative loads */
+	msr	SSBS, xzr
+cpu_reset_func_end cortex_x3
+
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
 	 */
 func cortex_x3_core_pwr_dwn
-#if ERRATA_X3_2313909
-	mov	x15, x30
-	bl	cpu_get_rev_var
-	bl	errata_cortex_x3_2313909_wa
-	mov	x30, x15
-#endif /* ERRATA_X3_2313909 */
-
+apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
 	/* ---------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------------
 	 */
-	mrs	x0, CORTEX_X3_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_X3_CPUPWRCTLR_EL1, x0
+	sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
 	isb
 	ret
 endfunc cortex_x3_core_pwr_dwn
 
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
-	mov	x0, #ERRATA_APPLIES
-#else
-	mov	x0, #ERRATA_MISSING
-#endif
-	ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_x3_reset_func
-	mov	x19, x30
-	/* Disable speculative loads */
-	msr	SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
-	/*
-	 * The Cortex-X3 generic vectors are overridden to apply
-	 * errata mitigation on exception entry from lower ELs.
-         */
-	adr	x0, wa_cve_vbar_cortex_x3
-	msr	vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
-	bl	cpu_get_rev_var
-
-#if ERRATA_X3_2615812
-	bl	errata_cortex_x3_2615812_wa
-#endif /* ERRATA_X3_2615812 */
-
-	isb
-	ret	x19
-endfunc cortex_x3_reset_func
-
-/* ----------------------------------------------------------------------
- * Errata Workaround for Cortex-X3 Erratum 2313909 on power down request.
- * This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------------------------
- */
-func errata_cortex_x3_2313909_wa
-	/* Check revision. */
-	mov	x17, x30
-	bl	check_errata_2313909
-	cbz	x0, 1f
-
-	/* Set bit 36 in ACTLR2_EL1 */
-	mrs	x1, CORTEX_X3_CPUACTLR2_EL1
-	orr	x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36
-	msr	CORTEX_X3_CPUACTLR2_EL1, x1
-1:
-	ret	x17
-endfunc errata_cortex_x3_2313909_wa
-
-func check_errata_2313909
-	/* Applies to r0p0 and r1p0 */
-	mov	x1, #0x10
-	b	cpu_rev_var_ls
-endfunc check_errata_2313909
-
-/* ----------------------------------------------------------------------
- * Errata Workaround for Cortex-X3 Erratum 2615812 on power-on.
- * This applies to revision r0p0, r1p0, r1p1 of Cortex-X3. Open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------------------------
- */
-func errata_cortex_x3_2615812_wa
-	/* Check revision. */
-	mov	x17, x30
-	bl	check_errata_2615812
-	cbz	x0, 1f
-
-	/* Disable retention control for WFI and WFE. */
-	mrs	x0, CORTEX_X3_CPUPWRCTLR_EL1
-	bfi	x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
-	bfi	x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
-	msr	CORTEX_X3_CPUPWRCTLR_EL1, x0
-1:
-	ret	x17
-endfunc errata_cortex_x3_2615812_wa
-
-func check_errata_2615812
-	/* Applies to r1p1 and below. */
-	mov	x1, #0x11
-	b	cpu_rev_var_ls
-endfunc check_errata_2615812
-
-#if REPORT_ERRATA
-	/*
-	 * Errata printing function for Cortex-X3. Must follow AAPCS.
-	 */
-func cortex_x3_errata_report
-	stp	x8, x30, [sp, #-16]!
-
-	bl	cpu_get_rev_var
-	mov	x8, x0
-
-	/*
-	 * Report all errata. The revision-variant information is passed to
-	 * checking functions of each errata.
-	 */
-	report_errata ERRATA_X3_2313909, cortex_x3, 2313909
-	report_errata ERRATA_X3_2615812, cortex_x3, 2615812
-	report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
-
-	ldp	x8, x30, [sp], #16
-	ret
-endfunc cortex_x3_errata_report
-#endif
+errata_report_shim cortex_x3
 
 	/* ---------------------------------------------
 	 * This function provides Cortex-X3-