diff options
| author | Bipin Ravi <bipin.ravi@arm.com> | 2023-09-18 17:27:29 -0500 |
|---|---|---|
| committer | Bipin Ravi <bipin.ravi@arm.com> | 2023-09-18 17:43:51 -0500 |
| commit | b01140256b5c0620cbde8e98c0df0e95343a3c71 (patch) | |
| tree | 5429297d689ee04b06add987d8c17f6d0ae76fc1 /lib/cpus/aarch64 | |
| parent | 8852fb5b7d94229475446c81cfa58851bc2204ff (diff) | |
fix(cpus): workaround for Neoverse V2 erratum 2719105
Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba
Diffstat (limited to 'lib/cpus/aarch64')
| -rw-r--r-- | lib/cpus/aarch64/neoverse_v2.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S index 83488274b..6c4adb12e 100644 --- a/lib/cpus/aarch64/neoverse_v2.S +++ b/lib/cpus/aarch64/neoverse_v2.S @@ -29,6 +29,12 @@ workaround_reset_end neoverse_v2, ERRATUM(2331132) check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) +workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 + sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 +workaround_reset_end neoverse_v2, ERRATUM(2719105) + +check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) + workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 /* dsb before isb of power down sequence */ dsb sy |