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authorSona Mathew <sonarebecca.mathew@arm.com>2023-10-12 12:04:53 -0500
committerSona Mathew <sonarebecca.mathew@arm.com>2023-10-24 14:35:21 -0500
commit6e86475d55fa2981bc342a0eb78b86be233d7718 (patch)
treea9f122ad4417c2cb6feec22397336cd347f3edef /lib/cpus/aarch64
parentd6b458e82a06d92a50b6a2abad7a835aabfa2686 (diff)
fix(cpus): workaround for Cortex-A510 erratum 2080326
Cortex-A510 erratum 2080326 is a Cat B erratum that applies to all revisions <= r0p2 and is fixed in r0p3. The workaround sequence helps perform a DSB after each TLBI instruction and can be applied only for version r0p2 and has minimal performance impact. The workaround is not applicable for versions < r0p2. SDEN documentation: https://developer.arm.com/documentation/SDEN1873361/latest Change-Id: Ib9bce8b711c25a79f7b2f891ae6f8b366fc80ddd Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Diffstat (limited to 'lib/cpus/aarch64')
-rw-r--r--lib/cpus/aarch64/cortex_a510.S24
1 files changed, 24 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 6fce24e02..a59b92c15 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -57,6 +57,30 @@ workaround_reset_end cortex_a510, ERRATUM(2042739)
check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2)
+workaround_reset_start cortex_a510, ERRATUM(2080326), ERRATA_A510_2080326
+ /* Apply workaround */
+ mov x0, #1
+ msr S3_6_C15_C4_0, x0
+ isb
+
+ mov x0, #0x0100
+ movk x0, #0x0E08, lsl #16
+ msr S3_6_C15_C4_2, x0
+
+ mov x0, #0x0300
+ movk x0, #0x0F1F, lsl #16
+ movk x0, #0x0008, lsl #32
+ msr S3_6_C15_C4_3, x0
+
+ mov x0, #0x03F1
+ movk x0, #0x00C0, lsl #16
+ msr S3_6_C15_C4_1, x0
+
+ isb
+workaround_reset_end cortex_a510, ERRATUM(2080326)
+
+check_erratum_range cortex_a510, ERRATUM(2080326), CPU_REV(0, 2), CPU_REV(0, 2)
+
workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148
/*
* Force L2 allocation of transient lines by setting