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authorBipin Ravi <bipin.ravi@arm.com>2023-10-17 06:21:15 -0500
committerlaurenw-arm <lauren.wehrmeister@arm.com>2023-11-02 10:12:36 -0500
commit68085ad4827ac7daa39767d479d0565daa32cb47 (patch)
tree814d4dede917f9275b7e1aa010b6930b21b37af1 /lib/cpus/aarch64
parent6cb8be17a53f4e11880ba13b78fca15895281cfe (diff)
fix(cpus): workaround for Neoverse N2 erratum 2340933
Neoverse N2 erratum 2340933 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR5_EL1[61] to 1. SDEN documentation: https://developer.arm.com/documentation/SDEN-1982442/latest Change-Id: I121add0dd35072c53392d33f049d893a5ff6354f Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Diffstat (limited to 'lib/cpus/aarch64')
-rw-r--r--lib/cpus/aarch64/neoverse_n2.S7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index f80115177..477522fed 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -165,6 +165,13 @@ workaround_runtime_end neoverse_n2, ERRATUM(2326639)
check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0)
+workaround_runtime_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933
+ /* Set bit 61 in CPUACTLR5_EL1 */
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61)
+workaround_runtime_end neoverse_n2, ERRATUM(2340933)
+
+check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0)
+
workaround_runtime_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952
/* Set TXREQ to STATIC and full L2 TQ size */
mrs x1, NEOVERSE_N2_CPUECTLR2_EL1