diff options
| author | Moritz Fischer <moritzf@google.com> | 2023-07-18 19:08:12 +0000 |
|---|---|---|
| committer | Arvind Ram Prakash <arvind.ramprakash@arm.com> | 2023-08-10 15:49:53 -0500 |
| commit | 5039015a9d610966df180bc8f94d582d13d2b3bf (patch) | |
| tree | 61e8ddd1e60bb672141feecb398202da13af5159 /lib/cpus/aarch64 | |
| parent | 31a3da83f81cb12d2940d90d04016323b45c9fde (diff) | |
refactor(cpus): convert Neoverse V2 to use CPU helpers
Convert Neoverse V2 to use CPU helpers, in this case that's
only two spots.
Change-Id: Icd250f92974e8a50c459038de7644a2e68007589
Signed-off-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Diffstat (limited to 'lib/cpus/aarch64')
| -rw-r--r-- | lib/cpus/aarch64/neoverse_v2.S | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S index 35dfa3750..36ae4deb7 100644 --- a/lib/cpus/aarch64/neoverse_v2.S +++ b/lib/cpus/aarch64/neoverse_v2.S @@ -35,8 +35,7 @@ workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 * The Neoverse-V2 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. */ - adr x0, wa_cve_vbar_neoverse_v2 - msr vbar_el3, x0 + override_vector_table wa_cve_vbar_neoverse_v2 #endif /* IMAGE_BL31 */ workaround_reset_end neoverse_v2, CVE(2022,23960) @@ -55,10 +54,7 @@ func neoverse_v2_core_pwr_dwn * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 - orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 - + sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 isb |