diff options
| author | Sona Mathew <sonarebecca.mathew@arm.com> | 2023-10-03 17:09:09 -0500 |
|---|---|---|
| committer | Sona Mathew <sonarebecca.mathew@arm.com> | 2023-10-04 13:45:16 -0500 |
| commit | 2454316c2ae4411d0071d88c3db3c95598f12498 (patch) | |
| tree | d0ca3c8c17905495cbc2a481f6b623f224597a79 /lib/cpus/aarch64 | |
| parent | 18b47a9ca4597091fbb62203fd107b52d65ac93b (diff) | |
fix(cpus): workaround for Cortex-X3 erratum 2070301
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Diffstat (limited to 'lib/cpus/aarch64')
| -rw-r--r-- | lib/cpus/aarch64/cortex_x3.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 98d148e2e..0cb3b976b 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -26,6 +26,13 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 #endif /* WORKAROUND_CVE_2022_23960 */ +workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 + sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ + CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH +workaround_reset_end cortex_x3, ERRATUM(2070301) + +check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) + workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB |