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| author | Bipin Ravi <bipin.ravi@arm.com> | 2023-08-11 21:16:14 +0200 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-08-11 21:16:14 +0200 |
| commit | 0a54b5cda5c7f3efde384ce7b23316bfc60687b7 (patch) | |
| tree | eb2204df95af0aeb06601079e392952e3c3c4b42 /lib/cpus/aarch64 | |
| parent | e0af991078601598bbc64f8c932bc84a2c47a3c0 (diff) | |
| parent | b98eb2dc1d49f5c279e236051d861a1deb7d0ef9 (diff) | |
Merge changes from topic "ar/errata_refactor" into integration
* changes:
refactor(cpus): convert Neoverse Poseidon to use CPU helpers
refactor(cpus): convert Neoverse Poseidon to framework
Diffstat (limited to 'lib/cpus/aarch64')
| -rw-r--r-- | lib/cpus/aarch64/neoverse_poseidon.S | 67 |
1 files changed, 20 insertions, 47 deletions
diff --git a/lib/cpus/aarch64/neoverse_poseidon.S b/lib/cpus/aarch64/neoverse_poseidon.S index 030293da0..3b3245d8e 100644 --- a/lib/cpus/aarch64/neoverse_poseidon.S +++ b/lib/cpus/aarch64/neoverse_poseidon.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,6 +26,19 @@ wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon #endif /* WORKAROUND_CVE_2022_23960 */ +workaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Neoverse-poseidon generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + override_vector_table wa_cve_vbar_neoverse_poseidon + +#endif /* IMAGE_BL31 */ +workaround_reset_end neoverse_poseidon, CVE(2022,23960) + +check_erratum_chosen neoverse_poseidon, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -35,59 +48,19 @@ func neoverse_poseidon_core_pwr_dwn * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 - orr x0, x0, #NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, x0 + sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \ + NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + isb ret endfunc neoverse_poseidon_core_pwr_dwn -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - -func neoverse_poseidon_reset_func +cpu_reset_func_start neoverse_poseidon /* Disable speculative loads */ msr SSBS, xzr +cpu_reset_func_end neoverse_poseidon -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Neoverse Poseidon generic vectors are overridden to apply - * errata mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_neoverse_poseidon - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret -endfunc neoverse_poseidon_reset_func - -#if REPORT_ERRATA - /* - * Errata printing function for Neoverse Poseidon. Must follow AAPCS. - */ -func neoverse_poseidon_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata WORKAROUND_CVE_2022_23960, neoverse_poseidon, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc neoverse_poseidon_errata_report -#endif +errata_report_shim neoverse_poseidon /* --------------------------------------------- * This function provides Neoverse-Poseidon specific |