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authorlaurenw-arm <lauren.wehrmeister@arm.com>2019-10-11 15:45:24 -0500
committerlaurenw-arm <lauren.wehrmeister@arm.com>2019-10-24 09:42:40 -0500
commit22cab65018487b1ea1838c48c7b6bae768a85e7e (patch)
treebc6ca647d6926af22be4d14c37c9ac94b26dcba3 /lib/cpus/aarch64/neoverse_n1.S
parenta04808c16cfc126d9fe572ae7c4b5a3d39de5796 (diff)
Fix white space errors + remove #if defined
Fix a few white space errors and remove #if defined in workaround for N1 Errata 1542419. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I07ac5a2fd50cd63de53c06e3d0f8262871b62fad
Diffstat (limited to 'lib/cpus/aarch64/neoverse_n1.S')
-rw-r--r--lib/cpus/aarch64/neoverse_n1.S12
1 files changed, 5 insertions, 7 deletions
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index c9bb005e3..faf53a848 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -21,9 +21,7 @@
#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-#if ERRATA_N1_IC_TRAP
.global neoverse_n1_errata_ic_trap_handler
-#endif
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Erratum 1043202.
@@ -356,7 +354,7 @@ func errata_n1_1542419_wa
bl check_errata_1542419
cbz x0, 1f
- /* Apply instruction patching sequence */
+ /* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
ldr x0, =0xEE670D35
@@ -536,10 +534,10 @@ func neoverse_n1_errata_ic_trap_handler
tlbi vae3is, xzr
dsb sy
- # Skip the IC instruction itself
- mrs x3, elr_el3
- add x3, x3, #4
- msr elr_el3, x3
+ # Skip the IC instruction itself
+ mrs x3, elr_el3
+ add x3, x3, #4
+ msr elr_el3, x3
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]